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ADC0808 ADC0809 8-Bit mP Compatible a D Converters With 8-Channel

ADC0808 ADC0809 8-Bit mP Compatible a D Converters With 8-Channel

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TLH5672
 A D C  0  8  0  8     A D C  0  8  0  9  8 - B  i    t  
   m
 P  C  o m  p a t   i    b  l    e A    D C  o n v e r  t   e r  s w i    t   h  8 - C  h  a n n e l    M u l    t   i     p l    e x e r 
November 1995
ADC0808ADC0809 8-Bit
m
P Compatible AD Converterswith 8-Channel Multiplexer
General Description
The ADC0808 ADC0809 data acquisition component is amonolithic CMOS device with an 8-bit analog-to-digital con-verter 8-channel multiplexer and microprocessor compati-ble control logic The 8-bit AD converter uses successiveapproximation as the conversion technique The converterfeatures a high impedance chopper stabilized comparator a256R voltage divider with analog switch tree and a succes-sive approximation register The 8-channel multiplexer candirectly access any of 8-single-ended analog signalsThe device eliminates the need for external zero and full-scale adjustments Easy interfacing to microprocessors isprovided by the latched and decoded multiplexer addressinputs and latched TTL TRI-STATE
outputsThe design of the ADC0808 ADC0809 has been optimizedby incorporating the most desirable aspects of several ADconversion techniques The ADC0808 ADC0809 offers highspeedhigh accuracy minimal temperature dependenceexcellent long-term accuracy and repeatability and con-sumes minimal powerThese features make this deviceideally suited to applications from process and machinecontrol to consumer and automotive applications For 16-channel multiplexer with common output (samplehold port)see ADC0816 data sheet (See AN-247 for more informa-tion)
Features
Y
Easy interface to all microprocessors
Y
Operates ratiometrically or with 5 V
DC
or analog spanadjusted voltage reference
Y
No zero or full-scale adjust required
Y
8-channel multiplexer with address logic
Y
0V to 5V input range with single 5V power supply
Y
Outputs meet TTL voltage level specifications
Y
Standard hermetic or molded 28-pin DIP package
Y
28-pin molded chip carrier package
Y
ADC0808 equivalent to MM74C949
Y
ADC0809 equivalent to MM74C949-1
Key Specifications
Y
Resolution 8 Bits
Y
Total Unadjusted Error
g

LSB and
g
1 LSB
Y
Single Supply 5 V
DC
Y
Low Power 15 mW
Y
Conversion Time 100
m
s
Block Diagram
TLH5672–1
TRI-STATE
is a registered trademark of National Semiconductor Corp
See OrderingInformation
C
1996 National Semiconductor Corporation RRD-B30M36Printed in USA
httpwwwnationalcom
 
Absolute Maximum Ratings
(Notes 1  2)
If MilitaryAerospace specified devices are requiredplease contact the National Semiconductor SalesOfficeDistributors for availability and specifications
Supply Voltage (V
CC
) (Note 3) 65VVoltage at Any Pin
b
03V to (V
CC
a
03V)Except Control InputsVoltage at Control Inputs
b
03V to
a
15V(START OE CLOCK ALE ADD A ADD B ADD C)Storage Temperature Range
b
65
C to
a
150
CPackage Dissipation at T
A
e
25
C 875 mWLead Temp (Soldering 10 seconds)Dual-In-Line Package (plastic) 260
CDual-In-Line Package (ceramic) 300
CMolded Chip Carrier PackageVapor Phase (60 seconds) 215
CInfrared (15 seconds) 220
CESD Susceptibility (Note 8) 400V
Operating Conditions
(Notes 1  2)Temperature Range (Note 1) T
MIN
s
T
A
s
T
MAX
ADC0808CJ
b
55
C
s
T
A
s
a
125
CADC0808CCJ ADC0808CCNADC0809CCN
b
40
C
s
T
A
s
a
85
CADC0808CCV ADC0809CCV
b
40
C
s
T
A
s
a
85
CRange of V
CC
(Note 1) 45 V
DC
to 60 V
DC
Electrical Characteristics
Converter Specifications
V
CC
e
5 V
DC
e
V
REF
a
V
REF(
b
)
e
GND T
MIN
s
T
A
s
T
MAX
and f
CLK
e
640 kHz unless otherwisestated
Symbol Parameter Conditions Min Typ Max Units
ADC0808Total Unadjusted Error 25
C
g

LSB(Note 5) T
MIN
to T
MAX
g

LSBADC0809Total Unadjusted Error 0
C to 70
C
g
1 LSB(Note 5) T
MIN
to T
MAX
g
1

LSBInput Resistance From Ref(
a
) to Ref(
b
) 10 25 k
X
Analog Input Voltage Range (Note 4) V(
a
) or V(
b
) GND
b
010 V
CC
a
010 V
DC
V
REF(
a
)
Voltage Top of Ladder Measured at Ref(
a
) V
CC
V
CC
a
01 VV
REF(
a
)
a
V
REF(
b
)
2VoltageCenter of Ladder V
CC
2-01 V
CC
2 V
CC
2
a
01 VV
REF(
b
)
Voltage Bottom of Ladder Measured at Ref(
b
)
b
01 0 VI
IN
Comparator Input Current f
c
e
640 kHz (Note 6)
b
2
g
05 2
m
A
Electrical Characteristics
Digital Levels and DC Specifications
ADC0808CJ 45V
s
V
CC
s
55V
b
55
C
s
T
A
s
a
125
C unless otherwise notedADC0808CCJ ADC0808CCN ADC0808CCV ADC0809CCN and ADC0809CCV 475
s
V
CC
s
525V
b
40
C
s
T
A
s
a
85
C un-less otherwise noted
Symbol Parameter Conditions Min Typ Max UnitsANALOG MULTIPLEXER
I
OFF(
a
)
OFF Channel Leakage Current V
CC
e
5V V
IN
e
5VT
A
e
25
C 10 200 nAT
MIN
to T
MAX
10
m
AI
OFF(
b
)
OFF Channel Leakage Current V
CC
e
5V V
IN
e
0T
A
e
25
C
b
200
b
10 nAT
MIN
to T
MAX
b
10
m
A
httpwwwnationalcom
2
 
Electrical Characteristics
(Continued)
Digital Levels and DC Specifications
ADC0808CJ 45V
s
V
CC
s
55V
b
55
C
s
T
A
s
a
125
C unless otherwise notedADC0808CCJ ADC0808CCN ADC0808CCV ADC0809CCN and ADC0809CCV 475
s
V
CC
s
525V
b
40
C
s
T
A
s
a
85
C un-less otherwise noted
Symbol Parameter Conditions MIn Typ Max UnitsCONTROL INPUTS
V
IN(1)
Logical 1Input Voltage V
CC
b
15 VV
IN(0)
Logical 0Input Voltage 15 VI
IN(1)
Logical 1Input Current V
IN
e
15V 10
m
A(The Control Inputs)I
IN(0)
Logical 0Input Current V
IN
e
0
b
10
m
A(The Control Inputs)I
CC
Supply Current f
CLK
e
640 kHz 03 30 mA
DATA OUTPUTS AND EOC (INTERRUPT)
V
OUT(1)
Logical 1Output Voltage I
O
eb
360
m
A V
CC
b
04 VV
OUT(0)
Logical 0Output Voltage I
O
e
16 mA 045 VV
OUT(0)
Logical ‘‘0’Output Voltage EOC I
O
e
12 mA 045 VI
OUT
TRI-STATE Output Current V
O
e
5V 3
m
AV
O
e
0
b
3
m
A
Electrical Characteristics
Timing Specifications
V
CC
e
V
REF(
a
)
e
5V V
REF(
b
)
e
GND t
r
e
t
f
e
20 ns and T
A
e
25
C unless otherwise noted
Symbol Parameter Conditions MIn Typ Max Units
t
WS
Minimum Start Pulse Width
(Figure 5) 
100 200 nst
WALE
Minimum ALE Pulse Width
(Figure 5) 
100 200 nst
s
Minimum Address Set-Up Time
(Figure 5) 
25 50 nst
H
Minimum Address Hold Time
(Figure 5) 
25 50 nst
D
Analog MUX Delay Time R
S
e
0
X
(Figure 5) 
1 25
m
SFrom ALEt
H1
 t
H0
OE Control to Q Logic State C
L
e
50 pF R
L
e
10k
(Figure 8) 
125 250 nst
1H
 t
0H
OE Control to Hi-Z C
L
e
10 pF R
L
e
10k
(Figure 8) 
125 250 nst
c
Conversion Time f
c
e
640 kHz
(Figure 5) 
(Note 7) 90 100 116
m
Sf
c
Clock Frequency 10 640 1280 kHzt
EOC
EOC Delay Time
(Figure 5) 
0 8
a
2
m
S ClockPeriodsC
IN
Input Capacitance At Control Inputs 10 15 pFC
OUT
TRI-STATE Output At TRI-STATE Outputs 10 15 pFCapacitance
Note 1
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not apply when operatingthe device beyond its specified operating conditions
Note 2
All voltages are measured with respect to GND unless othewise specified
Note 3
A zener diode exists internally from V
CC
to GND and has a typical breakdown voltage of 7 V
DC
Note 4
Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages one diode drop below ground or one diode dropgreater than the V
CC
n supply The spec allows 100 mV forward bias of either diode This means that as long as the analog V
IN
does not exceed the supply voltageby more than 100 mV the output code will be correct To achieve an absolute 0V
DC
to 5V
DC
input voltage range will therefore require a minimum supply voltage of4900 V
DC
over temperature variations initial tolerance and loading
Note 5
Total unadjusted error includes offset full-scale linearity and multiplexer errors See
Figure 3 
 None of these ADs requires a zero or full-scale adjustHowever if an all zero code is desired for an analog input other than 00V or if a narrow full-scale span exists (for example 05V to 45V full-scale) the referencevoltages can be adjusted to achieve this See
Figure 13 
Note 6
Comparator input current is a bias current into or out of the chopper stabilized comparator The bias current varies directly with clock frequency and haslittle temperature dependence
(Figure 6) 
 See paragraph 40
Note 7
The outputs of the data register are updated one clock cycle before the rising edge of EOC
Note 8
Human body model 100 pF discharged through a 15 k
X
resistor
httpwwwnationalcom
3

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