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11/21/2014

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KNCET, TRICHY Page 1
KONGUNADU COLLEGE OF ENGINEERING AND TECHNOLOGY ME-APPLIED ELECTRONICS AP 7201 ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS POSSIBLE QUESTIONS UNITI
1.

Explain the CS stage with Resistive load and Diode connected load and also explain the small signal equivalent circuit.

2.

Explain the CS stage with current source load, source degeneration and Triode load.

3.

Discuss on MOS folded Cascode and MOS active Cascode operational amplifiers

4.

With a neat sketch and explain the NMOS Cascode amplifier.

5.

Derive the voltage gain equation for source follower using NMOS transistor.

6.

Construct common gate stage and derive the voltage gain equation for CG.

7.

Derive the equation of source follower input impedance.

8.

With necessary diagrams, derive the equation for CMRR of differential amplifier with active load using FET 9.

Draw and explain the differential amplifier with MOS loads and calculate its gain 10.

Explain the single ended and differential operation. 11.

Derive the equation of the small-signal differential voltage gain of Differential pair. 12.

Calculate the voltage gain of the following circuits 13.

Write a short note on body effect and channel length modulation.

14.

Derive an expression for output resistance in CS stage with source degeneration.

15.

In the circuit of fig , (W/L )
1,2 ,3,4
= 50/0.5 and ISS =1mA . What is the small signal differential gain? For V
in,cm
= 1.5 V what is the maxium allowable output swing? 16.

Calculate the exact voltage gain of the circuit shown in below figure.

KNCET, TRICHY Page 2
17.

Calculate the output resistance (VX/IX) of the following circuits. Assume λ≠0 and γ≠0.
18.

In the circuit of fig. ,all transistors have a (W/L ) of 50/0.5 and M
3
and M
4
are to operate in deep triode region with an on resistance of 2 K
, Assuming I
d5

= 20 µA and λ = ϒ
= 0. Calculate the input common mode level that yields such resistance. Sketch V
out1
and V
out2
as V
in1
and V
in2
vary differentially from 0 to V
DD
.
UNIT-II
1.

Explain why Miller’s theorem cannot be applied to calculate the effect of the thermal noise of a floating resistor? 2.

Explain the high-frequency model of a Cascode stage.

3.

Derive the equations of the input impedance, output impedance and voltage gain of the common source stage.

4.

Derive the equations of the input impedance, output impedance and voltage gain of source follower.

5.

Construct common gate stage and derive the voltage gain equation for CG.

6.

Explain the statistical characteristics of noise.

7.

Write a short note on flicker noise.

8.

Write a short note on equivalent input noise generators.

9.

Find the maximum noise voltage that a single MOSFET can generate.

10.

Find the maximum thermal noise voltage that the gate resistance of a single MOSFET can generate and For a NMOS current source; calculate the total thermal and 1/f noise in the drain current for a band from 1 KHz to 1 MHz 11.

Explain types of noises and also give detail about noise in single stage amplifiers. 12.

Describe the noises in integrated circuits.

13.

Derive the expression of noise bandwidth. 14.

Calculate the input referred thermal noise voltage and current in fig.. Assume λ = ϒ
= 0

KNCET, TRICHY Page 3
15.

Calculate the noise spectrum and the total noise power in V
out
.
UNIT-III
1.

Explain the four types of feedback topologies. 2.

Explain about loading in voltage-voltage feedback and current voltage feedback and derive the voltage gain equation for both circuits. 3.

4.

Explain the noise in operational amplifiers.

5.

Compare the performance of various op amp topologies.

6.

Explain the following terms:

(i)

Gain (ii)

Small and Large signal Bandwidth (iii)

Output swing (iv)

Noise 7.

Explain the following terms:

(i)

Slew rate

(ii)

PSRR

(iii)

Unity gain buffer

(iv)

Gain boosting

8.

Discuss about the Input range limitations and gain boosting.

9.

The circuit of figure is designed for a nominal gain of 10. i.e., 1+R1/R2=10.Determine the minimum value of A1 for a gain error of 1%. 10.

Calculate the gain of the transconductance amplifier shown in fig.