Problem 2 (wider bus – 2words)
•
Block size = 4 word
•
Memory bus size = 2 word
•
Miss rate = 2.5%
•
Memory access per instruction = 1.2
•
Cache miss Penalty = 128 CC
•
Avg Cycles per instruction = 2
•
Interleaved Memory CPU Cache
64 CC
Assume 1000 instructions in your Program
If no miss then execution time is 2000 CC
. , ->
One instruction needs 1 2 memory accesses 1000 instruction 1200
. .%
accesses If miss rate is 2 5 then number of misses for 1200
.
accesses is 30
the execution time is
= + =
2000 30x128 5840 CC
= / = .
Average cycles per instruction 5840 1000 5 84