FIGURES & RESULTS:

PHASE OFFSETS


2GHZ PHASE ACCUMULATOR

SINE LUT MODULE

2GHZ DAC MODULE(MOCK)

RESULTS:


Simulation of 15 MHz single Core DDS


Phase of 15 MHz single Core DDS

RTL Schematic of DDS Single Core


Simulation Results of Single DDS Core using Xilinx ISE


15MHZ Sinusoidal output from DAC(Multi DDS)

15MHZ Output Phase of Sinusoidal Signal(Multi DDS)


RTL Schematic of 8 core DDS System

Simulation Results of 8 Core DDS System using Xilinx ISE


Simulation of 64 MHz signal

Phase of 64 MHz signal