2.1 LOGIC GATES We have seen that the foundation of logic design is seated in a well defined axiomatic system called Boolean algebra, which was shown to be what is known as a Huntington system. In this axiomatic system the definition of !" and #$ o%erators or functions was set forth and these were found to be well defined o%erators having certain %ro%erties that allow us to extend their definition to Hardware a%%lications. &hese !" and #$ o%erators, sometimes referred to as connectives, actually suggest a function that can be emulated by some H'w logic device. &he logic Hardware devices (ust mentioned are commonly referred to as gates. )ee% in mind that the usage of gate refers to an actual %iece of Hardware where function or o%eration refers to a logic o%erator !". #n the other hand, when we refer to a gate we are referring directly to a %iece of hardware called a gate. &he main %oint to remember is *"on+t confuse gates with logic o%erators+. 2.1.1 Basic Logic Gates Positive and egative Logic !esignation &he binary signals at the in%uts or out%uts of any gate can have one of the two values exce%t during transition. #ne signal levels re%resents logic , and the other logic -. .ince two signal values are assigned two to logic values, there exist two different assignments of signals to logic. /ogics , and - are generally re%resented by different voltage levels. 0onsider the two values of a binary signal as shown in 1ig. 2.3.,. #ne value must be higher than the other since the two values must be different in order to distinguish between them. We designate the higher voltage level by H and lower voltage level by /. &here are two choices for logic values assignment. 0hoosing the high4level 5H6 to re%resent logic , as shown in 5a6 defines a %ositive logic system. 0hoosing the low level / to re%resent logic4, as shown in 5b6, defines a negative logic system. Fig. 2.".1 &he terms %ositive and negative are somewhat misleading since both signal values may be %ositive or both may be negative. &herefore, it is not signal %olarity that determines the ty%e of logic, but rather the assignment of logic values according to the relative am%litudes of the signals. &he effect of changing from one logic designation to the other e7uivalent to com%lementing the logic functions because of the %rinci%le of duality of Boolean algebra. Gate !efinition *gate+ is defined as a multi4in%ut 58 26 hardware device that has a two4level out%ut. &he out%ut level 5,9H'-9/6 of the gate is a strict and re%eatable function of the two4level 5,9H'-9/6 combinations a%%lied to its in%uts. 1ig. 2.3.2 shows a general model of a gate. Fig. 2.".2 &he general model of a gate. &he term logic is usually used to refer to a decision making %rocess. logic gate, then, is a circuit that can decide to say yes or no at the out%ut based u%on in%uts. We a%%ly voltage as the in%ut to any gate, therefore the Boolean 5logic6 - and , do not re%resent actual number but instead re%resent the state of a voltage variable or what is called its logic level. .ometimes logic - and logic , may be called as shown in table below: Ta#le 2.".2 a. O$ Gate &he #$ gate is sometimes called the any or all gate. &o show the #$ gate we use the logical symbol in 1ig. 2.3.;5a6. b. c. Fig. 2.".% 5a6 #$ gate logic symbol . 5b6 <ractical #$ gate circuit. d. e. truth4table for the *#$+ gate is shown below according to 1ig. 2.3.;5b6. &he truth4table lists the switch and light conditions for the #$ gate. &he uni7ue out%ut from the #$ gate is a /#W only when all in%uts are low. &he out%ut column in &able 52.3.;6 shows that only the first line generates a - while all others are ,. Ta#le 2.".% f. g. 1ig. 2.3.;5c6 shows the ways to ex%ress that in%ut is #$ed with in%ut B to %roduce out%ut =. h. i. Fig. 2.".% 5c6 (. E&am'le. Determine the output Y from the OR gate for the given input waveform shown in Fig. 2.5.4(d). k. l. Fig. 2.".% 5d6 m. Solution. &he out%ut of an #$ gate is determined by reali>ing that it will be low only when both in%uts are low at the same time. 1or the in%uts the out%uts is low only during %eriod t2. In remaining time out%ut is , as shown in 1ig. 2.3.;5e6. n. o. Fig. 2.".% 5e6 %. We are now familiar with !" and #$ gates. t this stage, to illustrate at least in %art how a word statement can be formulated into a mathematical statement 5Boolean ex%ression6 and then to hardware network, consider the following exam%le: 7. E&am'le. t!arsha wi"" go to schoo" if #nand and $awan go to schoo"% or #nand and #&ush go to schoo". r. Solution. &his statement can be symboli>ed as a Boolean ex%ression as follows: s. t. &he next ste% is to transform this Boolean ex%ression into a Hardware network and this is where !" and #$ gates are used. u. v. &he out%ut of gate , is high only if both the in%uts and . are high 5mean both nandand .awan go to school6. &his is the first condition for ?tkarsha to go to school. w. &he out%ut of gate 2 is high only if both the in%uts and .= are high 5means both nand and yush go to school6. &his is the second condition for ?tkarsha to go to school. x. ccording to exam%le atleast one condition must be fullfilled in order that ?tkarsha goesto school. &he out%ut of gate @ is high when any of the in%ut to gate @ is high means at leastone condition is fulfilled or both the in%uts to gate @ are high means both the conditions are fulfilled. y. &he exam%le also demonstrates that nand has to go to school in any condition otherwise ?tkarsha will not go to school. >. #. A! Gate &he !" gate is sometimes called the all or nothing gate. &o show the !" gate we use the logic symbol in 1ig. 2.3.@5a6. &his is the standard symbol to memori>e and use from now on for !" gates. Fig. 2.".( 5a6 !" Aate logic symbol. 5b6 <ractical !" gate circuit. !ow, let us consider 1ig. 2.3.@5b6. &he !" gate in this figure is connnected to in%ut switches and B. &he out%ut indicator is an /B". If a low voltage 5Around, A!"6 a%%ears at in%uts, and B, then the out%ut /B" is not bit. &his situation is illustrated in table 56. /ine , indicates that if the in%uts are binary - and -, then the out%ut will be binary -. 'otice that on"& binar& ,s at both and B will %roduce a binary , at the out%ut. Ta#le 2.".( A! T)ut* Ta#le It is a C3D com%ared to A!" a%%earing at , B, or = that is called a binary , or a HIAH voltage. binary -, or /ow voltage, is defined as a A!" voltage 5near -D com%ared to A!"6 a%%earing at , B or =. (e are using positive "ogic because it ta!es a positive )5* to produce what we ca"" a binar& +. &he truth table is said to discribe the !" function. &he uni7ue out%ut from the !" gate is a HIAH only when all in%uts are HIAH. 1ig. 2.3.@ 5c6 shows the ways to ex%ress that in%ut is !"ed with in%ut B to %roduce out%ut =. Pulsed O'e)ation In many a%%lications, the in%uts to a gate may be voltage that change with time between the two logic levels and are called as %ulsed waveforms. In studying the %ulsed o%eration of an !" gate, we consider the in%uts with res%ect to each other in order to determine the out%ut level at any given time. 1ollowing exam%le illustrates this o%eration: E&am'le. Determine the output Y from the #'D gate for the given input waveform shown in Fig. 2.5.,(d). . Fig. 2.".( 5d6 Solution. &he out%ut of an !" gate is determined by reali>ing that it will be high only when both in%uts are high at the same time. 1or the in%uts the out%uts is high only during t@ %eriod. In remaining times, the out%uts is - as shown in 1ig. 2.3.@5e6. Fig. 2.".( 5e6 Fig. 2.".( 5e6 c. OT Gate In digital logic, an inverter or NOT gate is a logic gate which implements logical negation. The truth table is shown on the right. This represents perfect switching behavior, which is the defining assumption in Digital electronics. In practice, actual devices have electrical characteristics that must be carefully considered when designing inverters. In fact, the non-ideal transition region behavior of a CMO inverter ma!es it useful in analog electronics as a class " amplifier #e.g., as the output stage of an operational amplifier $%
NOT gates are often called inverters. A NOT gate's output signal is the opposite of its input signal. Note that the symbol of the NOT gate is the same as that of the buffer, except for the small circle near its output. Small circles at input or output lines of a gate's schematic symbol denote the fact that the signal is inverted. Input Output L H H L 2.1.2 +nive)sal Gates A! and O$ gates. &he !!" and !#$ gates are widely used and are readily available from most integrated circuit manufacturers. ma(or reason for the wides%read use of these gates is that they are both '-*.R$#/ gates, universal in the sense that both can be used for !" o%erators, #$ o%erators, as well as Inverter. &hus, we see that a com%lex digital system can be com%letely synthesi>ed using only !!" gates or !#$ gates. a. !!" Aate &he !!" gate is a !#& !", or an inverted !" function. &he standard logic symbol for the !!" gate is shown in 1ig. 52.3.Ea6. &he little invert bubble 5small circle6 on the right end of the symbol means to invert the out%ut of !". b. Fig. 2."., 5a6 !!" gate logic symbol 5b6 Boolean ex%ression for the out%ut of a !!" gate. 1igure 2.3.E5b6 shows a se%arate !" gate and inverter being used to %roduce the !!" logic function. lso notice that the Boolean ex%ression for the !" gate, 5.B6 and the !!" 5.B6are shown on the logic diagram of 1ig. 2.3.E5b6. &he truth4table for the !!" gate is shown in 1ig. 2.3.E5c6. &he truth4table for the !!" gate is develo%ed by inverting the out%ut of the !" gate. *&he uni7ue out%ut from the !!" gate is a /#W only when all in%uts are HIAH. c. d. Fig. 2."., 5c6 &ruth4table for !" and !!" gates. 1ig. 2.3.E 5d6 shows the ways to ex%ress that in%ut is !!"ed with in%ut B yielding out%ut =. e. f. Fig. 2."., 5d6 E&am'le. Determine the output Y from the '#'D gate from the given input waveform shown in Fig. 2.0.1 (e). g. h. Fig. 2."., 5e6 Solution. &he out%ut of !!" gate is determined by reali>ing that it will be low only when both the in%uts are high and in all other conditions it will be high. &he ou%ut = is shown in 1ig. 2.3.E5f6. i. (. Fig. 2."., 5f6 T*e A! gate as a +I-E$SAL Gate &he chart in 1ig. 2.3.E5g6 shows how would you wire !!" gates to create any of the other basic logic functions. &he logic function to be %erformed is listed in the left column of the tableF the customary symbol for that function is listed in the center column. In the right column, is a symbol diagram of how !!" gates would be wired to %erform the logic function. k. l. Fig. 2."., 5g6 m. T*e O$ gate. &he !#$ gate is actually a !#& #$ gate or an inverted #$ function. n. &he standard logic symbol for the !#$ gate is shown in 1ig. 2.3.E5h6 o. %. Fig. 2."., 5h6 !#$ gate logic symbol 5i6 Boolean ex%ression for the out%ut of !#$ gate. !ote that the !#$ symbol is an #$ symbol with a small invert bubble on the right side. &he !#$ function is being %erformed by an #$ gate and an inverter in 1ig. 2.3.E5i6. &he Boolean function for the #$ function is shown 5 C B6, the Boolean ex%ression for the final !#$ function is 5 C B6. 7. &he truth4table for the !#$ gate is shown in 1ig. 2.3.E526. !otice that the !#$ gate truth table is (ust the com%lement of the out%ut of the #$ gate. &he uni7ue out%ut from the !#$ gate is a HIAH only when all in%uts are /#W. r. s. Fig. 2."., 526 &ruth4table for #$ and !#$ gates. t. 1igure 2.3.E5!6 shows the ways to ex%ress that in%ut is #$ed with in%ut B yielding u. out%ut =. v. w. x. Fig. 2."., 5!6 y. E&am'le. Determine the output Y from the 'OR gate from the given input waveform shown in Fig. 2.5.1("). >. aa. Fig. 2."., 5"6 bb.Solution. &he out%ut of !#$ gate is determined by reali>ing that it will be HIAH only when both the in%uts are /#W and in all other conditions it will be high. &he out%ut = is shown in 1ig. 2.3.E5m6. cc. dd.Fig. 2."., 5m6 B . O$ Gate T*e O$ gate as a +I-E$SAL gate. &he chart in 1ig. 2.3.E5n6 shows how would your wire !#$ gates to create any of the other basic logic functions. Fig. 2."., 5n6 2.1.( Coincidence gates a. T*e E&clusive O$ Gate &he exclusive #$ gate is sometimes referred to as the #dd but not the even gate. It is often shortend as G#$ gate. &he logic diagram is shown in 1ig. 2.3.H 5a6 with its Boolean ex%ression. &he symbol means the terms are G#$ed together. Fig. 2.".. 5a6 &he truth table for G#$ gate is shown in 1ig. 2.3.H 5b6. !otice that if any but not all the in%uts are ,, then the out%ut will be ,. *&he uni7ue characteristic of the G#$ gates that it %roduces a HIAH out%ut only when the odd no. of HIAH in%uts are %resent.+ Fig. 2.".. 5b6 &o demonstrate this, 1ig. 2.3.H 5c6 shows a three in%ut G#$ gate logic symbol and the truth table 1ig. 2.3.H 5d6. &he Boolean ex%ression for a three in%ut G#$ gate can be written as Fig. 2.".. 5c6 Fig. 2.".. 5d6 <utting the value of G, we get = I 5BC B60 C 5BC B6.0 = I B0C B0C B0 C B0 &he HIAH out%uts are generated only when odd number of HIAH in%uts are %resent 5see &.&.6 34his is wh& 5OR function is a"so !nown as odd function6. 1ig. 2.3.H 5e6 shows the ways to ex%ress that in%ut is G#$ed with in%ut B yielding out%ut =. Fig. 2.".. 5e6 &he G#$ gate using !" #$4!#& gates. we know B I BC B s we know !!" and !#$ are universal gates means any logic diagram can be made using only !!" gates or using only !#$ gates. /O$ gate using A! gates onl0. G#$ using !#$ gates only. &he %rocedure for im%lementing any logic function using only universal gate 5only !!" gates or only !#$ gates6 will be treated in detail in section 2.J.
E&am'le. Determine the output Y from the 5OR gate from the given input waveform shown in Fig. 2.5.7 (f). Fig. 2.".. 5f6 Solution. &he out%ut G#$ gate is determined by reali>ing that it will be HIAH only when the odd number of high in%uts are %resent therefore the out%ut = is high for time %eriod t2 and t3 as shown in 1ig. 2.3.H 5g6. #. T*e E&clusive O$ gate c. d. &he Bxclusive !#$ gate is sometimes reffered to as the *0#I!0I"B!0B+ or *BK?ID/B!0B+ gate. &his is often shortened as *G!#$+ gate. &he logic diagram is shown in 1ig. 2.3.L 5a6. e. f. Fig. 2.".1 5a6 g. #bserve that it is the G#$ symbol with the added invert bubble on the out%ut side. &he Boolean ex%ression for G!#$ is therefore, the invert of G#$ function denoted by symbol #. h. i. (. &he truth table for G!#$ gate is shown in 1ig. 2.3.L 5b6. k. l. Fig. 2.".1 5b6 m. !otice that the out%ut of G!#$ gate is the com%lement of G#$ truth table. n. *&he uni7ue out%ut of the G!#$ gate is a /#W only when an odd number of in%ut are HIAH+. o. %. Fig. 2.".1 5c6 7. r. Fig. 2.".1 5d6 s. &o demonstrate this, 1ig. 2.3.L 5c6 shows a three in%ut G!#$ gate logic symbol and the truth4table 2.3.L 5d6. t. 1igure 2.3.L 5e6 shows the ways to ex%ress that in%ut is G!#$ed with in%ut B yielding u. out%ut =. v. w. x. Fig. 2.".1 5e6 y. !ow at this %oint, it is left as an exercise for the reader to make G!#$ gate using !"#$4!#& gates, using !!" gates only and using !#$ gates only. >. E&am'le. Determine the output Y from the 5'OR gate from the given input waveform shown in Fig. 2.5.8 (f). aa. bb.Fig. 2.".1 5f6 cc. Solution. &he out%ut of G!#$ gate is determined by reali>ing that it will be HIAH only when the even4number of high in%uts are %resent, therefore the out%ut = is high for time %eriod t2 and t3 as shown in 1ig. 2.3.L 5g6. dd. ee.F ig. 2.".1 5g6 ff. a.T*e E&clusive O$ gate &he Bxclusive !#$ gate is sometimes reffered to as the *0#I!0I"B!0B+ or *BK?ID/B!0B+ gate. &his is often shortened as *G!#$+ gate. &he logic diagram is shown in 1ig. 2.3.L 5a6. gg. hh.Fig. 2.".1 5a6 ii. #bserve that it is the G#$ symbol with the added invert bubble on the out%ut side. &he Boolean ex%ression for G!#$ is therefore, the invert of G#$ function denoted by symbol #. ((. kk. ll. &he truth table for G!#$ gate is shown in 1ig. 2.3.L 5b6. mm. nn.Fig. 2.".1 5b6 oo. !otice that the out%ut of G!#$ gate is the com%lement of G#$ truth table. %%.*&he uni7ue out%ut of the G!#$ gate is a /#W only when an odd number of in%ut are HIAH+. 77. rr. Fig. 2.".1 5c6 ss. tt. Fig. 2.".1 5d6 uu.&o demonstrate this, 1ig. 2.3.L 5c6 shows a three in%ut G!#$ gate logic symbol and the truth4table 2.3.L 5d6. vv. 1igure 2.3.L 5e6 shows the ways to ex%ress that in%ut is G!#$ed with in%ut B yielding ww.out%ut =. xx. yy. >>. Fig. 2.".1 5e6 aaa.!ow at this %oint, it is left as an exercise for the reader to make G!#$ gate using !"#$4!#& gates, using !!" gates only and using !#$ gates only. bbb.E&am'le. Determine the output Y from the 5'OR gate from the given input waveform shown in Fig. 2.5.8 (f). ccc. ddd.Fig. 2.".1 5f6 eee.Solution. &he out%ut of G!#$ gate is determined by reali>ing that it will be HIAH only when the even4number of high in%uts are %resent, therefore the out%ut = is high for time %eriod t2 and t3 as shown in 1ig. 2.3.L 5g6. fff. ggg.F ig. 2.".1 5g6 hhh. 2.2 L OGIC !IAG$A2 "re diagrams in the field of logic, used for representation and to carry out certain types of reasoning. Basic Logic Diagrams &asic logic diagrams are used to show the operation of a particular unit or component. &asic logic symbols are shown in their proper relationship so as to show operation only in the most simplified form possible. 'igure (-)* shows a basic logic diagram for a serial subtractor. The operation of the unit is described briefly in the ne+t paragraph. In the basic subtractor in figure (-)*, assume you want to subtract binary ,%% #decimal %- from binary %,, #decimal *-. "t time Io, the , input at " and % input at & of inhibitor I% results in a , output from inhibitor I% and a % output from inhibitor I). The , output from I% and the % output from I) are applied to O. gate /%, producing a % output from /%. The % output from I) is also applied to the delay line. The I output from /% along with the , output from the delay line produces % output from I0. The % input from /% and the , input from the delay line produce a , output from inhibitor I*. The , output from 1 and the % output from I0 are applied to O. gate /) producing a % output. t time t, the - in%uts on the and B in%ut lines of I, %roduce - out%uts from I, and I2. &he - in%uts on both in%ut lines of #$ gate A, result in a - out%ut from A,. &he I in%ut a%%lied to the delay line at time to emerges 5, bit time delay6 and is now a%%lied to the inhibit line of ,@ %roducing an - out%ut from I@. &he , out%ut from the delay line is also a%%lied to inhibitor I;, and along with the - out%ut from A, %roduces a , out%ut from I;. &he I; out%ut is recycled back into the delay line, and also a%%lied to #$ gate A2. s a result of the - and , in%uts from I@, and I;, #$ gate A2 %roduces a , out%ut. t time t2, the , in%ut on the line and the - in%ut on the B line of I, %roduce a , out%ut from I, and a - out%ut from I2. &hese out%uts a%%lied to #$ gate A, %roduce a , out%ut from A,, which is a%%lied to ,@ and I;. &he delay line now %roduces a , out%ut 5recycled in at time t,6, which is a%%lied to I@ and I;. &he , out%ut from the delay line along with the , out%ut from A, %roduces a - out%ut from I@. &he , out%ut from A, along with the , out%ut from the delay line %roduces a - out%ut from I;. With - out%uts from I@ and I;, #$ gate A2 %roduces a - out%ut.
2.( T)ut* Ta#le " truth table shows how a logic circuit2s output responds to various combinations of the inputs, using logic % for true and logic , for false. "ll permutations of the inputs are listed on the left, and the output of the circuit is listed on the right. The desired output can be achieved by a combination of logic gates. " truth table for two inputs is shown, but it can be e+tended to any number of inputs. The input columns are usually constructed in the order of binary counting with a number of bits e3ual to the number of inputs. Truth table for most commonly used logical operators 4ere is a truth table giving definitions of the most commonly used 5 of the %( possible truth functions of ) binary variables #6,7 are thus boolean variables- 8 PQ & & & & 1 & & & & & 1 1 & & 1 1 & 1 1 & 1 & & 1 & 1 1 1 1 1 1 1 & & & & 9ey8 & I true, 1 I false I !" 5logical con(unction6 I #$ 5logical dis(unction6 I G#$ 5exclusive or6 I G!#$ 5exclusive nor6 I conditional Mif4thenM I conditional M5then64ifM biconditional or Mif4and4only4ifM is logically e7uivalent to : G!#$ 5exclusive nor6. Condensed truth tables for binary operators 'or binary operators, a condensed form of truth table is also used, where the row headings and the column headings specify the operands and the table cells specify the result. 'or e+ample &oolean logic uses this condensed truth table notation8 3F T F 1 1 T 1 & 4F T F 1 & T & & This notation is useful especially if the operations are commutative, although one can additionally specify that the rows are the first operand and the columns are the second operand. This condensed notation is particularly useful in discussing multi-valued e+tensions of logic, as it significantly cuts down on combinatoric e+plosion of the number of rows otherwise needed. It also provides for 3uic!ly recogni:able characteristic ;shape; of the distribution of the values in the table which can assist the reader in grasping the rules more 3uic!ly. Truth tables in digital logic Truth tables are also used to specify the functionality of hardware loo!-up tables #1<Ts- in digital logic circuitry. 'or an n-input 1<T, the truth table will have )=n values #or rows in the above tabular format-, completely specifying a boolean function for the 1<T. &y representing each boolean value as a bit in a binary number, truth table values can be efficiently encoded as integer values in electronic design automation #>D"- software. 'or e+ample, a 0)-bit integer can encode the truth table for a 1<T with up to ? inputs. @hen using an integer representation of a truth table, the output value of the 1<T can be obtained by calculating a bit inde+ k based on the input values of the 1<T, in which case the 1<T2s output value is the kth bit of the integer. 'or e+ample, to evaluate the output value of a 1<T given an array of n boolean input values, the bit inde+ of the truth table2s output value can be computed as follows8 if the ith input is true, let Ai B %, else let Ai B ,. Then the kth bit of the binary representation of the truth table is the 1<T2s output value, where k B A,C)=, D A%C)=% D A)C)=) D ... D AnC)=n. Truth tables are a simple and straightforward way to encode boolean functions, however given the e+ponential growth in si:e as the number of inputs increase, they are not suitable for functions with a large number of inputs. Other representations which are more memory efficient are te+t e3uations and binary decision diagrams. Applications of truth tables in digital electronics In digital electronics #and computer science, fields of engineering derived from applied logic and math-, truth tables can be used to reduce basic boolean operations to simple correlations of inputs to outputs, without the use of logic gates or code. 'or e+ample, a binary addition can be represented with the truth table8 A B | C R 1 1 | 1 0 1 0 | 0 1 0 1 | 0 1 0 0 | 0 0 where A = First Operand B = Second Operand C = Carry R = Result This truth table is read left to right8 Dalue %air 5,B6 e7uals value %air 50,$6. #r for this exam%le, %lus B e7ual result $, with the 0arry 0. Eote that this table does not describe the logic operations necessary to implement this operation, rather it simply specifies the function of inputs to output values. In this case it can only be used for very simple inputs and outputs, such as %2s and ,2s, however if the number of types of values one can have on the inputs increases, the si:e of the truth table will increase. 'or instance, in an addition operation, one needs two operands, " and &. >ach can have one of two values, :ero or one. The number of combinations of these two values is )+), or four. o the result is four possible outputs of C and .. If one was to use base 0, the si:e would increase to 0+0, or nine possible outputs. The first ;addition; e+ample above is called a half-adder. " full-adder is when the carry from the previous operation is provided as input to the ne+t adder. Thus, a truth table of eight rows would be needed to describe a full adder2s logic8 A B C* | C R 0 0 0 | 0 0 0 1 0 | 0 1 1 0 0 | 0 1 1 1 0 | 1 0 0 0 1 | 0 1 0 1 1 | 1 0 1 0 1 | 1 0 1 1 1 | 1 1 Same as previous !ut"" C* = Carry #rom previous adder 2.4 CIRCUIT MAKING In order to play with TTL gates, you must have several pieces of equipment. Here's a list of what you will need to purchase: breadboard volt-ohm meter !also "nown as a multimeter# logic probe !optional# regulated 5-volt power supply collection of TTL chips to e$periment with %everal LEDs !light emitting diodes# to see outputs of the gates %everal resistors for the L&'s %ome wire !() to (* gauge# to hoo" things together These parts together might cost +etween ,-) and ,.) or so, depending on where you get them. Let's wal" through a few details on these parts to ma"e you more familiar with them: s descri+ed on the previous page, a breadboard is a device that ma"es it easy to wire up your circuits. volt-ohm meter lets you measure voltage and current easily. /e will use it to ma"e sure that our power supply is producing the right voltage. The logic probe is optional. It ma"es it easy to test the state !0 or )# of a wire, +ut you can do the same thing with an L&'. 1f the parts descri+ed a+ove, all are easy e$cept the 5-volt power supply. 2o one seems to sell a simple, cheap 34volt regulated power supply. 5ou therefore have two choices. 5ou can either +uy a surplus power supply from 6ameco !for something li"e a video game# and use the 34volt supply from it, or you can use a little power4cu+e transformer and then +uild the regulator yourself. /e will tal" through +oth options +elow. n LED !light emitting diode# is a mini light +ul+. 5ou use L&'s to see the output of a gate. /e will use the resistors to protect the L&'s. If you fail to use the resistors, the L&'s will +urn out immediately. This equipment is not the sort of stuff you are going to find at the corner store. However, it is not hard to o+tain these parts. 5ou have a few choices when trying to purchase the components listed a+ove: ,. 7adio %hac" A resistor and an LED 2. local electronics parts store 4 8ost ma9or cities have electronics parts stores, and many cities are +lessed with good surplus electronics stores. If you can find a good surplus store in your area that caters to people +uilding their own stuff, then you have found a goldmine. @. mail4order house li"e 6ameco 4 6ameco has +een in +usiness for decades, has a good inventory and good prices. !:e sure to download their ;'< catalog or get a paper catalog from them 44 it ma"es it much easier to traverse the /e+ site.# The following ta+le shows you what you need to +uy, with 6ameco part num+ers listed. ;art Jameco # Breadboard ()=(( olt-ohm meter 00>(0( Logic probe !optional# 0->>?) !egulated 5-volt power supply %ee +elow "#$$ !22' gates# -*>=> "#$% !217 gates# ->)03 "#$# !21T gates# ->)-) "#$& !2' gates# ->0-. "#'% !17 gates# 3)(?3 "#&( !@17 gates# 3)..3 5 to )$ LEDs >-3(>A 5 to )$ ''$-ohm resistors ?)*.= *ire !() to (* gauge# ?.=.= <or the ;ower %upply +optional, !%ee ne$t section for details# ;art Jameco # Trans-ormer != to 0( volts, ?))ma# 0->>.- "&$5 5-volt voltage regulator !T14(() case# 30(.( % #"$-micro-arad electrolytic capacitors >?*0=