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(SoC). Digitally generated noise corrupts supply voltages and is propagated inside a silicon substrate as so called substrate noise. A discussion and simplified analysis of passive and active circuits for substrate noise suppression is presented in this paper. An example of an active circuit is design and tested by means of simulations. The achieved results show higher efficiency of the active circuits in substrate noise attenuation in comparison to knownpassive solutions.
In resent years many complicated electronic systems are realized as a system on a chip (SoC). SoCs have many advantages, to mention a few: high degree of miniaturization, low power consumption, high speed, good reliability, and low cost of high volume fabrication. These possible advantages over multi integrated circuits implementation demand high experience from a designer, and taking into account problems related to interactions of many functional blocks on the same silicon substrate. Because of very large scale of integration and complicated nature of modern SoCs, sometimes it is difficult to correctly predict and avoid problems with interferences between functional blocks, which may cause degradation of SoC performance. The verification tests conducted on fabricated experimental chips reveal problems with correct functioning of some SoCs. The interactions between noisy digital and sensitive analog sub-circuits are frequently a reason for excessive noise and result in performance degradation of mixed signal systems . Even in uniform digital circuits, interferences between functional blocks may cause problems, like increased jitter of a system clock, variation in buffers delay or false bit generation . The common reason for all the mentioned problems is too strong coupling between sub-circuits placed close to each other on the same substrate. The analysis of future trends in CMOS technology and package evolution  predict problems in future SoCs. In a typical SoC three basic categories of system noise can be distinguished: noise on power/ground supply rails, substrate noise , , and crosstalk between signal lines. The power supply or ground noise arises when a sub-circuit generates supply current pulses of short rise and fall times. Such short pulses cause voltage drop on positive and voltage bounce on negative supply lines due to voltage drop on series parasitic resistances and inductances of the lines. Because the supply rails are very strongly coupled to a silicon substrate, a significant portion of supply noise is
also transferred to the substrate and it becomes substrate noise. The research in the resent decade enabled better understanding of the main mechanisms of noise generation and propagation ,  as well as possible prevention methods -. Unfortunately, the prevention methods designed for early, relatively small and slow SoCs may become inefficient in future very fast systems. It is because there exists some fundamental limitations in further reduction of parasitic coupling inside a common substrate and in minimization of resistances and inductances of the supply lines and package leads. The limitations of the commonly used methods for noise suppression can be alleviated by using active circuits. The active suppression circuits - seem to be promising alternative to the passive circuits in efficient noise suppression.
In this paper a short discussion about passive and active circuits for noise suppression is presented in the second section. The next section presents an example of an improved active circuit design together with simulation results. The final section contains discussion and conclusions.
The series parasitic resistances and inductances of power supply rails and on-chip interconnections biasing guard rings on a substrate are limiting factors for system noise reduction. In the case of functional blocks placed close to the edge of a chip, the interconnections parasitic impedance can almost be reduced to value of package impedance by using short and wide metal paths. A more difficult situation is with blocks located away from chip bond wire pads, where relatively long on-chip interconnects increase the total series impedance. For such blocks the total series resistance and inductance less than 10-20\ue000 and 10-20nH is difficult to achieve without using sophisticated and expensive packages. An interesting alternative to the application of expensive packages and using very wide
on-chip interconnection paths is the generation of local signals that compensate substrate noise or the generation of a low impedance ground inside a chip. The first compensation technique - is able to efficiently suppress substrate noise at relatively low frequencies up to 50-100MHz range. The technique uses operational amplifiers to create a compensation signal shifted in phase by 180O. By proper injection of the compensation signal into a substrate, noise can be significantly attenuated in the vicinity of the guard rings. The technique is only efficient at low frequencies due to limitations of the amplifier gain bandwidth. The second technique, based on the generation of a low impedance ground, has better frequency characteristics. Such technique has a potential ability to provide a high quality ground even for low quality packages and long on-chip interconnects. The published circuits using that technique are based mainly on operational amplifier or current conveyor architectures and also suffers from the frequency limitation. Impulsive supply noise, generated by fast switching digital circuits, with short rise and fall times is very badly attenuated by that kind of circuits .
In order to design improved active circuits for noise suppression it is crucial to understand weaknesses of the known circuits and specify fundamental requirements for better solutions. The active circuits for noise suppression designed in a SoC can only have speed characteristics similar to digital sub-circuits placed on the same substrate. The most abrupt supply/ground current pulses are generated by the fastest digital gate, which is an inverter. The supply current pulses of very short rise and fall times generated by the inverters can only be suppressed by a circuit as fast as inverters. Any other slower amplifiers, as for example multi-stage operational amplifiers or current conveyors, will not be able to deal with such pulses and they may additionally worsen the system noise performance due to potential instability and ringing effects caused by parasitic resonances of the on-chip supply network.
To explain basic requirements for the active noise suppression circuits, in view of commonly used passive suppression circuits, two simple models of decoupling configurations are presented in Fig. 1 and 2. In the figures the passive and active decoupling circuits are presented. The system noise is represented by the voltage sourceVn, which is coupled via the coupling capacitorCc to a signal line. The coupling capacitor can represent coupling between on-chip interconnections or it can represent a simplified case of coupling via a silicon substrate. The part of system noise coupled to the signal line is labeled asVc. To reduce noise level on the signal line, the decoupling capacitor is connected to it. The decoupling capacitor is represented by series capacitanceCd and resistanceRd to improve modeling accuracy at high frequencies. Additionally,RwandLw represent parasitic resistance and inductance of package leads, bond wires and an on-chip ground line. In the simple passive decoupling circuit, shown in Fig. 1, the decoupling capacitor is connected between the on-chip ground and the signal line. The active decoupling, modeled in Fig. 2, uses an operational amplifier with a
feedback loop to improve efficiency of noise suppression. A real operational amplifier is modeled by a frequency dependent controlled voltage source of gain
decoupling capacitor is connected in a negative feedback loop. Due to the Miller effect, the equivalent capacitance seen from the inverting input of the amplifier is greater than the decoupling capacitanceCd, and overall efficiency of the circuit is increased.
The efficiency of the discussed circuits is dependent on magnitude of the equivalent decoupling impedanceZdec, which forms with the coupling capacitanceCc a voltage divider. For the considered models, noise voltage on the signal line can be calculated as
boundary of noise suppression is mainly limited by the package, bond wire and on-chip interconnection impedances. For the considered configuration the lower limits for noise suppression are
It is important to notice that the passive decoupling is completely inefficient at high frequencies above the resonant frequency of the supply network, where the on-chip ground network behaves as inductance. This property makes the passive noise suppression highly inefficient at frequencies above 0.5-1GHz in typical SoCs. It is also worth to notice that large on-chip decoupling capacitance does not guarantee good noise grounding. It can only provide local suppression of differential mode noise, whereas common mode noise remains attenuated , .
In order to better understand the important tradeoffs of the active circuit design let us consider a simple two stage amplifier consisting of the first voltage gain stage and the second low-resistance output buffer. For a typical CMOS amplifier GB and the output resistance
and the drain current of the output buffer.D andE are constants specific to selected CMOS technology and the amplifier architecture. According to (3a) and (3b), the improvement of noise suppression requires an enlargement of the amplifier voltage gain\ue000 \ue001
and limited supply power the two requirements are contradictory. In order to find the optimal solution the decoupling impedance (3b) is expressed in terms of the total supply current
The expression (5) can be used as an object of optimization for a selected amplifier architecture and technology. A typical plot of the impedance magnitude is presented in Fig. 3 for 0.35\ue006m CMOS technology and a constant supply power
Two families of characteristics are presented in Fig. 3. The dashed lines labelled\ue000 refer to a two-stage amplifier with the input stage composed of nMOS transistors with the aspect ratio 100/0.35 and the output nMOS source follower of 100/0.35. The second family
buffer of 8000/0.35. The characteristics are plotted for three frequencies 50MHz, 300MHz, and 1GHz which is close to the gain bandwidth of the amplifiers. For the first amplifier a local minimum of the decupling impedance is observed when about 60% of the total supply current flows into the output buffer. The second amplifier provides much lower decoupling impedance and has relatively flat characteristics. For all considered cases the decoupling capacitor is assumed to have
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