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Modelling and evaluation of substrate noise induc

Modelling and evaluation of substrate noise induc

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Modelling and evaluation of substrate noise induced
by interconnects
F. Martorell, D. Mateo and X. Aragone` s
Abstract:Interconnects have received attention as a source of crosstalk to other interconnects, but

have been ignored as a source of substrate noise. The importance of interconnect-induced substrate noise is evaluated in this paper. A known interconnect and substrate model is validated by comparing simulation results to experimental measurements. Based on the validated modelling approach, a complete study considering frequency, geometrical, load and shielding effects is presented. The importance of interconnect-induced substrate noise is demonstrated after observing that, for typically sized interconnects and state-of-the-art speeds, the amount of coupled noise is already comparable to that injected by hundreds of transistors. The need to include high-frequency effects in the model is also discussed, together with accuracy trade-offs.

1 Introduction

Coupling through the silicon substrate in submicron integrated circuits is known to be a severe source of problems and performance limitation. The trend towards SoC integration, where highly sensitive analogue sections including RF receivers, GHz oscillators and huge digital processing sections coexist in the same die, increases concern about this problem. As a consequence, there is an urgent demand for accurate CAD tools which allow prediction of substrate noise limitations at the design stage. These tools must take into account the most important mechanisms of noise injection to the substrate in current and near-future technologies. In the last decade there has been an effort to determine the most signi\ufb01cant sources of substrate noise[1, 2] and provide models and extraction tools for them[3 \u2013 5]. Nevertheless, as signal frequencies move into microwave ranges, the sources of noise and models must be revisited, and the extraction tools adapted to the new conditions.

In recent years, tools which extract substrate parasitics have been commercialised, and their performance and accuracy are being progressively improved. These tools are often based on the \ufb01nite-difference method, and obtain a substrate model consisting of a mesh of impedances between circuit-substrate ports. The mesh of impedances can then be included as a subcircuit in a netlist for a full-circuit analogue simulation. The extracted substrate mesh includes ports wherever a noise injection or reception point is expected. These are usually transistors and substrate contacts. Other noise injection points are commonly ignored, although their importance has not been demonstrated to be negligible.

These include coupling from large metal areas like
capacitors, pads and interconnects.

Intuition suggests that long interconnect lines driving GHz switching clocks may be a signi\ufb01cant source of noise coupled to substrate, and that coupling between these interconnects and substrate is worth modelling. Up to now, there has been no known numerical study evaluating this source of coupling. In this paper, we model this coupling with a RC distributed interconnect model linked to a substrate mesh extracted with SubstrateStorme[6]. The interconnect-substrate model has been validated by comparing with measurements on test structures.

2 Modelling coupling from interconnects

Substrate extraction tools based on the \ufb01nite-difference method obtain a model consisting of a mesh of impedances between circuit ports. In circuit extraction, interconnects are usually modelled ideally as a single node, in the best of cases capacitively coupled to ideal ground. Here, we wish to couple the interconnects to the substrate mesh, and we use the classical distributed R-C model illustrated inFig. 1 [7], which is now referenced to substrate instead of ideal GND. Each interconnect segment of lengthDLis instanced as two serial resistorsR and a capacitanceC coupled to a port of the substrate model. The values ofR andC can be computed from geometrical and technology information, as

R\u00bc RA
DL=2
W
C\u00bc CareaDL\u00c1 W\u00fe Cperim2DL
\u00f01\u00de

whereDLand Ware the length and width of the segment, RA is the sheet resistance, andCarea andCperim are respectively the area and perimeter capacitances. The distributed RC model does not include high-frequency effects such as inductance or skin-effect. Their importance will be discussed later in this paper.

We have implemented our proposed interconnect model in the \ufb02ow of the substrate extraction tool SubstrateStorme from Cadence[6], using a 0.35mm technology design kit.

qIEE, 2003
IEE Proceedingsonline no. 20030828
doi: 10.1049/ip-cdt:20030828

The authors are with the Electronic Engineering Dept., Universitat Polite`cnica de Catalunya Campus Nord. Edi\ufb01ci C4. Jordi Girona, 1-3. 08034 Barcelona (Spain)

Paper received 19th May 2003
IEE Proc.-Comput. Digit. Tech., Vol. 150, No. 5, September 2003
338Authorized licensed use limited to: University of Central Florida. Downloaded on November 8, 2008 at 21:29 from IEEE Xplore. Restrictions apply.

This tool extracts a substrate model consisting of a mesh of resistances between access ports, which is valid for frequencies up to some GHz. We have created new layout layers which allow us to de\ufb01ne which interconnects we wish to extract, and the segment divisions in each interconnect. The extraction rules \ufb01le was modi\ufb01ed to identify the selected interconnects and to save important geometrical data. From these data, the resistance and capacitance values were computed according to (1). Then, each interconnect segment was associated to the instance model inFig. 1, where theR andC are parameterised to the values computed. We also de\ufb01ned the operation of SubstrateStorme to create substrate ports associated to every interconnect segment instance. As a result, we were able to extract the substrate parasitics of any circuit including coupling from interconnects, and to control the accuracy (number of segments) of the interconnect model.

3 Validation of the substrate-interconnect model

The former modelling approach has been validated by comparing AC analysis simulations to experimental measurements on three test structures.

3.1 Description of the test structure
Figure 2shows a photograph of the test structures

manufactured in a 3-metal, 0.35mm technology. The substrate is high-resistive (10V\u00b7cm resistivity), except for a shallow channel-stopper outside active regions. The structures consist of 500mm long interconnects, connected at both ends to pads to allow probe access. The interconnects are (left to right) 1mm wide in metal-1 layer, 1mm wide in metal-3, and 10mm wide in metal-1, respectively. Near every interconnect there are two 60\u00c2 60mm2pads, upon which coupling will be sensed. The pad at the right (A) of every line is contacted to the substrate, i.e. allows measurement of noise on the substrate surface.

The pads at the left (B) of the lines have no direct contact to the substrate, and are coupled only through their parasitic capacitance. The pads have been accessed with GSG probes and consequently are escorted by two other pads connected to ground, as seen inFig. 2. The whole structure is enclosed inside a grounded ring of substrate contacts.

3.2 Measurementresults

A HP 8510C network analyser and Picoprobe 40A-150- GSG probes were used to measure S-parameters between line ends and the nearby pads. From these measurements, the voltage gain (coupling) between the input and output pads is derived by using Mason\u2019s rule[8], and imposing

ZL\u00bcZs \u00bcZO\u00bc50O: This leads to the simple expression:
AV\u00bcVout
Vin\u00bcS21
1\u00feS11
\u00f02\u00de

This voltage gain determines the amount of noise that reaches the sensor pad (out) coupled through the substrate from the interconnect (in). This voltage gain is compared to that obtained from AC circuit simulations of the test structures extracted as described in Section 2, including a 50V load at the sensor pad to account for the impedance of the measurement equipment. The parasitic capacitances of all the pads, including those connected to ground, have also been extracted and coupled to the substrate model. Coupling capacitances for the pads and the interconnect model have been obtained from geometrical and technological data with the help of a 2D electromagnetic \ufb01eld solver[9]. Also, a substrate resistivity pro\ufb01le has been reconstructed from the manufacturer\u2019s data.

Figure 3shows the measurement results compared

against simulation results for the three test structures, when the far end of the interconnect is left open circuit. Two sets of measurements and simulations are represented, one in which the output is the pad with an ohmic connection to the substrate, and another in which the output is the pad coupled to the substrate through its parasitic capacitance. An excellent agreement between simulation and measure- ments is veri\ufb01ed. The agreement is lost for frequencies near 10 GHz, where the validity of the purely resistive substrate model is lost, and the interconnect starts to acquire transmission-line behaviour.

Measurements with the open line present a high re\ufb02ection coef\ufb01cient which may lead to inaccurate results. This does not seem to be the case here since measurements were performed on different samples and in different days, giving very little dispersion in all cases. Probe-to-probe coupling

Fig. 1Equivalent circuit model for an interconnect coupled to
substrate
Fig. 2Test structures implemented in a 0.35mm technology to
measure coupling from interconnects
Fig. 3Voltage coupled from the interconnects to the sensor pads
(interconnect is open-ended)
IEE Proc.-Comput. Digit. Tech., Vol. 150, No. 5, September 2003
339
Authorized licensed use limited to: University of Central Florida. Downloaded on November 8, 2008 at 21:29 from IEEE Xplore. Restrictions apply.

was also veri\ufb01ed to be about 30 dB below the substrate coupling. In spite of this, we repeated the measurements, this time loading the far end of the interconnect with 50V with the help of a third probe. Results are shown inFig. 4, again showing excellent agreement with the simulations. Please note that bothFig. 3 andFig. 4 represent voltages at the sensor pads relative to the voltage at the interconnect input (i.e., relative coupling). This is the reason why the curves in

Fig. 3and Fig. 4look similar, although in fact absolute
voltages were larger in the unloaded interconnect case.

Both inFig. 3 andFig. 4, a sustained increase of noise coupling with frequency is observed, due to the capacitive nature of the coupling, up to frequencies around 5 GHz. Then, coupling saturates to a level between 40 mV and 15 mV for a 1 V excitation, depending on the interconnect characteristics. These are fairly large noise levels taking into account that the output nodes are low-impedance (due to the 50V probe connection).

4 Interconnect coupling quanti\ufb01cation
4.1 Relative noise level in the substrate

Once the modelling approach has been validated, we extend the range of situations studied and quantify the importance of substrate noise induced by interconnects compared to other noise sources. We continue using the layout of the structures studied in the preceding Section, but now remove all the pads except for the two output ones.Figure 5 represents a sketch of the resulting layout. All the remaining

elements have been extracted and simulated in the same
accuracy conditions as in the preceeding Section.

Circuit extractions for 1-mm wide and 10-mm wide interconnects laid in metal-1, metal-2 and metal-3 are made. These extractions are simulated in an AC analysis, with the interconnect driving a realistic load consisting of four basic inverters of the 0.35mm technology used. Noise is sensed on the pad with an ohmic connection to the substrate, which is equivalent to measuring the noise level in the substrate at the pad location.Figure 6 shows the curves obtained, now in a linear scale so as to better appreciate the magnitude of the coupling.

Several observations may be drawn from these curves. Firstly, lines with higher capacitance to the substrate (wider interconnect, lower metal layer) present higher coupling levels. Secondly, and most importantly, coupling levels increase from very low levels for tone frequencies below 100 MHz to surprisingly high values at frequencies around and above 1 GHz. The exact coupling levels (up to 50% of the signal in the interconnect) may be a consequence of the particular layout or loading effect, as discussed in Section 5. Nevertheless, the overall observation is that, for tone frequencies above GHz, interconnects couple a very important fraction of their voltage to the substrate, which does not happen for frequencies in the MHz range. Appreciable tones of 10 GHz are already found in 2 GHz clocks[10], and tones of 2 GHz are present in clocks well below 400 MHz. Moreover, multi-GHz tones are common in CMOS RF ICs, where substrate coupling is also a concern. Thus, it may be concluded that in contemporary technologies, interconnects induce substrate noise with an intensity that was not known years ago.

4.2 Interconnect-induced noise against
transistor-induced noise

The results inFig. 6 suggest that interconnects are an important source of substrate noise, particularly in the GHz range. Nevertheless, to give real signi\ufb01cance to these numbers, a comparison with other noise sources should be provided. To compare with noise injected by active devices, we have replaced the line with an array of 200 inverters simultaneously switching. The inverters are minimum-size

\u00f0W=LNMOS\u00bc1=0:3;W=LPMOS\u00bc2:5=0:3\u00de:We drive the

transistors with a square signal having 0.1 ns rise/fall time, 1.6ns period, 3.3V amplitude. The noise injected is compared against the noise injected by lines 1mm wide and 500mm long, in different metal layers. Given that transistor-induced noise is coupled from output drains, we

Fig. 4Voltage coupled from the interconnects to the sensor pads
(interconnect is 50V loaded)
Fig. 5Layout of the basic test structure used in the simulations
Fig. 6Noise levels coupled to substrate when a 1 V signal is
applied to lines of different widths and metal layers
IEE Proc.-Comput. Digit. Tech., Vol. 150, No. 5, September 2003
340Authorized licensed use limited to: University of Central Florida. Downloaded on November 8, 2008 at 21:29 from IEEE Xplore. Restrictions apply.

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