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SRAM Leakage Suppression by
SRAM Leakage Suppression by
Minimizing Standby Supply Voltage
Minimizing Standby Supply Voltage
Huifang Qin, Yu (Kevin) Cao, Dejan Markovic,
Huifang Qin, Yu (Kevin) Cao, Dejan Markovic,
Andrei Vladimirescu, and Jan Rabaey
Andrei Vladimirescu, and Jan Rabaey
Berkeley Wireless Research Center,
University of California, Berkeley
-2 -
ISQED 2004
H. Qin
Outline
\ue000Motivations
\u2013SRAM leakage suppression for ultra-low power applications
\u2013Exploring Ultra-Low Voltage (ULV) SRAM operation capability
\ue000Modeling
\u2013The SRAM Data Retention Voltage (DRV)
\ue000Design and Implementation
\u2013Dual-rail leakage suppression scheme with ultra-low standby Vdd
\ue000Measurement Results and Analysis
\u2013To Minimize the SRAM DRV
\ue000Conclusion and Future Work
-3 -
ISQED 2004
H. Qin
Target application:
Ultra-Low Power (ULP) wireless sensor network
Motivation I: Leakage Suppression of Embedded SRAM
\ue000Nowadays the embedded SRAM circuits in a
microprocessor system typically consumes:

\u201390% of the total processor transistor count
\u201360% of the chip area
\u201320% ~ 50% of chip power

\ue000Power-efficient design is critical for portable electronics
\u2013To extend battery life requires maximum power savings. Even more
demanding is to enable energy scavenging
\u2013100% of ULP system leakage power?
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