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9, SEPTEMBER 2008
Abstract—In an SRAM circuit, the leakage currents on the bit in the nanometer technology. According to the report of [1],
lines are getting increasingly prominent with the dwindling of the worst-case bit-line leakage current can reach 117 A
transistors’ threshold voltages as the technology scales down to under high temperature and large column height. Because the
90 nm and beyond. Excessive bit-line leakage current results in
slower read operations or even functional failure. In this paper, non-evaluating bit-line is discharged by the bit-line leakage
we present a new technique, called X-calibration, to combat this current, the effective bit-line voltage swing developed by the
phenomenon. Unlike the previous method that attempts to com- cell current of the accessed memory cell during a read op-
pensate the leakage current directly, this scheme first transforms eration will decline. The degraded effective bit-line voltage
the bit-line leakage current into an equilibrium offset voltage swing either increases the delay of the sense amplifier or makes
across the bit-line pair, and then simple circuitry is utilized to
cancel this offset accurately at the input of the sense amplifier
the sense amplifier react incorrectly. Several methods have
so that the sensing is not affected by the bit-line leakage. SPICE been proposed to solve this problem. These methods can be
simulation of a 1 Kbit SRAM macro shows that this X-calibration classified into two categories: leakage suppression [2]–[4] and
scheme can handle 83% higher bit-line leakage current than the leakage compensation [5]–[7]. These studies try to solve the
previous bit-line leakage compensation scheme. Measurement problem by means of either adapting the manufacturing process
results of the test chip show that the SRAM macro adopting
or changing the circuitry.
X-calibration scheme can cope with up to 320 A bit-line leakage
current. The negative word-line scheme proposed in [2] forces an
inactive word-line to a voltage level lower than the ground to
Index Terms—Bitline leakage current, on-off ratio, sense ampli-
fier, SRAM, X-calibration scheme.
reduce the leakage through access transistors. Yet, this scheme
may still suffer from the so-called gate-induced drain leakage
current. The scheme proposed in [3] uses both dual threshold
I. INTRODUCTION voltage and aggressive biasing on the word-lines, the bit-lines,
and the power lines of the storage cells to curb the leakage
A S CMOS process technology scales down into the
nanometer scale, a number of unexpected side effects,
such as raised leakage current of transistors, larger process
currents. Hence, this scheme can cope with excessive bit-line
leakage current in a 100-nm dual- technology as demon-
variation, worse matching of symmetric devices, and deterio- strated [3]. However, as technology advances, the leakage
rated power and ground lines, start to emerge. These nanometer current could become even more severe and thus this leakage
effects not only bring enormous challenges to circuit designers suppression technique may still need some compensating
but also greatly reduce the manufacturing yield. Consequently, techniques that help to tolerate the leakage currents in addition
to design a robust circuit to deal with these effects has become to curbing them in the future. Also, as the process variation
much more important. increases, the biasing circuits may not be able to generate the
For logic circuits, the threshold voltage of transistors is often bias voltages as accurately. In [4], a dynamic leakage cut-off
reduced to retain high performance as the supply voltage de- scheme was also proposed. The drawback is that this scheme
clines. In turn, the reduced threshold voltage results in increased may degrade the operation speed due to the large additional
leakage current, which does not lead to catastrophic results for time required for generating a reverse substrate bias.
logic circuits. Yet, the raised leakage current could not only de- The bit-line compensation (BLC) scheme described in [5]
grade the performance for an SRAM circuit but also lead to er- modifies the pre-charge circuitry to detect the amount of the
roneous operations. bit-line leakage. After that, similar amount of current is injected
Bitline leakage current is the most significant component into the bit-line so as to compensate the loss due to leakage. Nev-
of leakage in memories and will become increasingly large ertheless, this scheme is sensitive to the process variation due to
the dynamic current mirror structure, which is extremely sus-
ceptive to the variation of the threshold voltage. The modified
Manuscript received April 13, 2007; revised April 25, 2008. Current version
BLC schemes described in [1] and [6] attempt to overcome some
published September 10, 2008. This work was supported by the National Sci- weaknesses in [5] such as the mismatch problem of the dynamic
ence Council of Taiwan under Grant NSC 96-2220-E-007-028. current mirror. The modified circuit proposed by [6] success-
The authors are with the Department of Electrical Engineering, Na-
tional Tsing Hua University, Hsinchu, Taiwan 30013, R.O.C. (e-mail:
fully uses the same transistor to detect the bit-line leakage cur-
yclai@larc.ee.nthu.edu.tw; d935916@oz.nthu.edu.tw). rent and inject the compensation current. Notwithstanding, the
Digital Object Identifier 10.1109/JSSC.2008.2001937 gate voltage of the transistor that decides the injected amount
0018-9200/$25.00 © 2008 IEEE
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LAI AND HUANG: X-CALIBRATION: A TECHNIQUE FOR COMBATING EXCESSIVE BITLINE LEAKAGE CURRENT IN NANOMETER SRAM DESIGNS 1965
Authorized licensed use limited to: University of Central Florida. Downloaded on October 26, 2008 at 00:04 from IEEE Xplore. Restrictions apply.
1966 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 9, SEPTEMBER 2008
A. Basic Concept
We regard the bit-line leakage current as an offset voltage
and then cancel the offset voltage by means of the calibration
circuitry attached to the sense amplifier. This basic idea can be
explained in two parts, as follows.
• Generation of the equilibrium offset voltage: The bit-line
leakage current is transformed into an offset voltage across
the bit-line pair. As shown in Fig. 3, we use the conven-
tional bit-line static load circuitry to provide pull-up cur-
rent against the bit-line leakage current. Finally, the voltage
level of each bit-line reaches an equilibrium level after
some time. The difference of the equilibrium levels across
the bit-line pair is referred to as the equilibrium offset
voltage or simply the offset voltage for the rest of this
paper.
Fig. 5. (a) Waveforms of the bit-line pair and input pair of the sense amplifier.
• Cancellation of the offset voltage: The offset voltage men- (b) Timing diagram of the control signals.
tioned above is first recorded and then cancelled by the
calibration circuitry attached to the inputs of the sense am-
plifier as shown in Fig. 3. The detailed operations of the
in Fig. 5(a). This scheme is called X-calibration because of the
calibration circuitry will be described later.
crossing structure formed by the switches controlled by .
The operation of an SRAM column with the calibration cir-
B. Circuit Architecture and Operation
cuitry can be divided into the following three phases, shown in
The schematic of the calibration circuitry shown in Fig. 4 is Fig. 5(a).
mainly composed of several switches and two coupling capac- 1) Pre-charge phase: In this phase, the bit-line pair is pre-
itors. There are two additional control signals, and , the charged to an initial level (namely in the design) and
timing diagrams of which are shown in Fig. 5(b). The transient the input pair of the sense amplifier is left floating. At this
waveforms of the bit-line pair and the input pair of the sense am- moment, all switches in the calibration circuitry are turned
plifier in the presence of the bit-line leakage current are shown off.
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LAI AND HUANG: X-CALIBRATION: A TECHNIQUE FOR COMBATING EXCESSIVE BITLINE LEAKAGE CURRENT IN NANOMETER SRAM DESIGNS 1967
Fig. 6. Illustration of each operation phase. (a) Pre-charge and equalization. (b) Detection. (c) Calibration and read.
2) Detection phase: The pre-charge circuit is turned off and by . At the end of this phase, the equilibrium offset voltage
the switches controlled by are turned on to detect the across the bit-line pair has been generated and stored in the cali-
offset voltage developed by the bit-line static load. Note bration circuitry. Finally, the column comes into the calibration
that this offset voltage has been flipped around by the and read phase shown in Fig. 6(c). The cell current discharges
crossing structure of the switches controlled by . This the complementary bit-line so that the voltage level of the com-
reversal of the offset voltage is designed intentionally to plementary bit-line falls down and balances at the voltage level
support easy offset cancellation later. of 1.45 V. This voltage drop can be transferred to the comple-
3) Calibration and read phase: The switches controlled by mentary input of the sense amplifier by means of the coupling
are turned off and then those controlled by are turned capacitor. Now, we can clearly see that the offset voltage is per-
on to couple the voltages at the bit-lines to the inputs of fectly cancelled at the input pair of the sense amplifier from
the sense amplifier. At the beginning of this phase, the re- Fig. 6(c).
versed offset voltage detected in phase 2 was stored across The sense amplifier we used is the latch-type sense amplifier
the bottom nodes of the two coupling capacitors and will mentioned in [8] and [9]. In order to use capacitive coupling to
be deducted from the differential voltage across the bit-line achieve the offset cancellation, the input impedance of a sense
pair to cancel out the offset voltage during this coupling amplifier must be infinite and the inputs of sense amplifier need
process. Therefore, the offset voltage disappears from the to be floating during the calibration phase. In addition, the ca-
input pair of the sense amplifier in this phase and the oper- pacitance of the coupling capacitor should be selected appropri-
ation performed by the sense amplifier will not be affected ately. If its capacitance is too small, the coupling effect will be
at all by the bit-line leakage. too weak and the offset voltage cancellation will be less accu-
Since the operation of the calibration is hidden within the rate. On the other hand, using too large capacitance will cause
read operation, there is no access time penalty in this scheme. excessive area overhead. Therefore, the selection of the capac-
Also, the calibration circuitry works well for the write operation. itance of the coupling capacitor is a tradeoff between coupling
The timings of the two control signals ( and ) should not efficiency and area. In our design, the capacitance of the cou-
overlap each other. pling capacitor is determined according to simulation result and
In order to clearly demonstrate the three operation phases of consideration of physical implementation.
an SRAM column with the calibration circuitry, we give an ex-
ample with bit-line leakage, as shown in Fig. 6. For simplicity,
IV. TRANSIENT ANALYSIS AND CHIP IMPLEMENTATION
each node’s voltage designated in Fig. 6 is just an approximate
value and thus slightly different from the real case. In Fig. 6(a),
A. Transient Analysis of X-Calibration Scheme
the column is in the pre-charge phase and the bit-line pair is
pre-charged and equalized to initial voltage level, 1.8 V. Then, in Fig. 7 shows transient waveforms of bit-lines under diverse
Fig. 6(b), the column gets into the detection phase. The bit-line bit-line leakage currents during a read operation, where BL is
voltage level drops down and eventually balances at the lower discharged by bit-line leakage current and /BL is discharged by
voltage level of 1.4 V due to the bit-line leakage current. This cell current when WL is turned on. The entire read cycle can
voltage level is carried to the bottom node of the coupling ca- be divided into three phases: 1) pre-charge; 2) detection; and
pacitor on the other side through the crossing switch controlled 3) calibration and read. Because the detection time borrows the
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1968 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 9, SEPTEMBER 2008
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LAI AND HUANG: X-CALIBRATION: A TECHNIQUE FOR COMBATING EXCESSIVE BITLINE LEAKAGE CURRENT IN NANOMETER SRAM DESIGNS 1969
TABLE I
COMPARISONS OF POWER, DELAY, AND MAXIMUM TOLERANT BIT-LINE LEAKAGE
V. EXPERIMENTAL RESULTS
A. Simulation Results
In order to compare the X-calibration scheme with the pre-
vious bit-line leakage compensation (BLC) scheme [5], we also
implemented an SRAM macro of 1 Kb using the circuit ar-
Fig. 12. Impact of bit-line leakage on access time for the three SRAM macros
chitecture of the BLC scheme. Table I lists the read current, in a 0.18-m CMOS technology with extra bit-line loading capacitance of
the write current, the access time, and the maximum tolerable (a) 200 fF and (b) 500 fF, respectively.
bit-line leakage of these three SRAM macros. These circuit per-
formance parameters are obtained by running SPICE simula-
tion. The following is the meaning of each column of Table I. small as compared with the SRAM macro with a large column
• Read current: The average supply current for performing a height, e.g., 256 or 512. As a result, we added extra loading ca-
read operation during one cycle. pacitance on each bit-line pair and run SPICE simulation for the
• Write current: The average supply current for performing three SRAM macros when deriving the data.
a write operation during one cycle. The experimental results show that the X-calibration scheme
• Access time: The delay from the rising edge of the clock can handle 61% and 83% higher bit-line leakage current than
to the transition edge of the data output during a read the BLC scheme under 200 fF and 500 fF extra bit-line loading
operation. capacitance, respectively. In addition, when the extra bit-line
• Maximum tolerable bit-line leakage: The maximum toler- loading capacitance increases, the upper bound of the bit-line
able bit-line leakage current under which the SRAM circuit leakage current that all SRAM macros can cope with will
can operate correctly. decline. However, the X-calibration scheme can still function
The impact of the bit-line leakage current on the access time correctly up to 300 A bit-line leakage current, as shown in
for each of the three SRAM macros is shown in Fig. 12. In prac- Fig. 12(b).
tice, there is cell current distribution due to process variation or The size of the critical transistors of both BLC and X-cali-
noise emerging on the bit-line pair. Therefore, the upper bound bration scheme may influence the experimental results, so we
of bit-line leakage for the conventional SRAM macro could be use similar dimensions for those transistors in both schemes
lower. Because the number of memory cells on each column for so as to guarantee fair comparison. The critical transistors for
these SRAM macros is 32, the bit-line loading capacitance is too BLC scheme refer to those for detecting bit-line leakage and for
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1970 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 9, SEPTEMBER 2008
TABLE II
RELATIONSHIP BETWEEN BIAS AND BIT-LINE LEAKAGE
TABLE III
TEST CHIP CHARACTERISTICS
Fig. 13. Relationship between the sensing time and the column height under Fig. 14. Shmoo plots of supply voltage versus BIAS for (a) conventional
(a) the room temperature 25 C and (b) a higher temperature 125 C for a 22-nm SRAM macro and (b) X-calibration SRAM macro.
CMOS technology.
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LAI AND HUANG: X-CALIBRATION: A TECHNIQUE FOR COMBATING EXCESSIVE BITLINE LEAKAGE CURRENT IN NANOMETER SRAM DESIGNS 1971
bit-line leakage current. Compared with the conventional 1 Kb Ya-Chun Lai was born in Taiwan in 1981. He re-
SRAM macro, the area overhead of the SRAM macro using the ceived the B.S. degree in electrical engineering from
X-calibration scheme is only 7.55%. Moreover, if the column National Tsing Hua University, Hsinchu, Taiwan,
R.O.C., in 2004, where he is currently working
height increases or the area of the coupling capacitor decreases, toward the Ph.D. degree in electrical engineering.
the area overhead can be reduced further. The measured extra He was a summer intern with Taiwan Semicon-
ductor Manufacturing Company, Ltd., in 2005. His
power consumption due to this scheme is only 9.7% at the recent research interests include VLSI design and
operating frequency of 150 MHz. Measurement results of the high-yield SRAM design for nanometer technology.
fabricated test chip validate that the X-calibration scheme is
not only feasible but also capable of increasing the maximum
tolerable bit-line leakage current up to 320 A, which is 4.18
times as much as in the conventional SRAM macro. Shi-Yu Huang (S’93–M’97) received the B.S. and
M.S. degrees in electrical engineering from National
Taiwan University, Taipei, Taiwan, R.O.C., in 1988
and 1992, and the Ph.D. degree in electrical and com-
ACKNOWLEDGMENT puter engineering from the University of California at
Santa Barbara in 1997, respectively.
He joined the faculty of the Department of Elec-
The authors would like to thank National Chip Implemen- trical Engineering, National Tsing-Hua University,
tation Center (CIC) and L.-M. Denq for technical support, Taiwan, in 1999, where he is currently an Associate
Taiwan Semiconductor Manufacturing Company (TSMC) for Professor. His research interests are mainly in VLSI
design, automation, and testing, with an emphasis on
chip fabrication, and M.-F. Chang and C.-W. Wu for their power estimation, fault diagnosis, CMOS image sensor design, and nanometer
valuable discussions. SRAM design.
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