Ex. No.

: PSUEDO RANDOM SEQUENCE GENERATOR

Date:

AIM:
To generate the pseudo random sequence using linear feedback shift register
and verify the output using truth table in bread board and HDL software.

APPARATUS REQUIRED:

DFF(IC 7484)
XOR (IC 7486)
Digital Trainer kit
Connecting wires
Personal Computer with Windows operating system
Xilinx 14.3 software

PROCEDURE:

Hardware:
Connections are made as per the circuit diagram.
Logic inputs are given as per the circuit diagram.
Observe the output and verify the truth table.

Simulation:

Write and draw the Digital logic system and write the Verilog code for above
system.
Enter the Verilog code in Xilinx software.
Check the syntax and simulate the above verilog code (using Xilinx) and
verify the output waveform as obtained.

THEORY:
PRBS generator generates pseudo random binary sequence based on the
concept of linear feedback shift register.It is pseudo because it is deterministic
and after n elements it starts to repeat itself, unlike real random sequences.
Random numbers for polynomial equations are generated by using the shift
register circuit. The random number generator is nothing but the Linear Feedback
Shift Register(LFSR). The shift registers are very helpful and versatile modules that
facilitate the design of many sequential circuits whose design may otherwise appear
very complex. In its simplest form, a shift register consists of a series of flip-flops
having identical interconnection between two adjacent flip-flops. Two such registers
are shift right registers and the shift left registers. In the shift right register, the bits
stored in the flip-flops shift to the right when shift pulse is active. Like that, for a
shift left register, the bits stored in the flip-flops shift left when shift pulse is active.
In the shift registers, specific patterns are shifted through the register. There are
applications where instead of specific patterns, random patterns are more important.
For a 4-bit PRBS generator, LFSR consist of 4-registers connected together as a
shift register. Here, we used D flipflop as a register. The input to the first register
comes from the XOR of third and fourth output bits of the register. The inputs fed
to the XOR are called the tap sequence and are often specified with
characteristic polynomial. On reset the register must be initialized to a non zero
value(all 1s).The output sequences through all 2^n-1 combinations when clock
signal is given. Obviously, its possible to get a longer m-sequence using more stages
to the shift register. The formula connecting these is: m=2^n-1.Where m is the
length of the m-sequence and n is the number of shift register stages. The
pseudo-random sequences are handy for built-in-test and bit-error-rate testing
in communication links. They are also used in many spread spectrum
communications systems such as GPS and CDMA and encoding and decoding the
error control codes. LFSRs used as a generators of pseudorandom sequences have
proved externally useful in the area of testing of VLSI chips.

Logic Diagram:













Verilog Coding:

module prbs(q,qb,clk,clr);
output [3:0] q,qb;
input clk,clr;
reg [3:0] tmp, tmpb;
always @(negedge clk or posedge clr)
begin
if(clr)
begin
tmp = 4'b1111;
tmpb = 4'b0000;
end
else
tmp = { tmp[3],tmp[2],tmp[1], tmp[3]^tmp[2]};
end
assign q=tmp;
assign qb=tmpb;
endmodule




















RESULT:
Thus the operation pseudo-random number was verified using hardware and
software simulations

Ex. No.: ARITHMETIC LOGIC UNIT DESIGN
Date:

AIM:
To design the Arithmetic Logic Unit using logic gates and HDL software.
APPARATUS REQUIRED:

IC7408
IC7411
IC7432
XOR (IC 7486)
Digital Trainer kit
Connecting wires
Personal Computer with Windows operating system
Xilinx 14.3 software

PROCEDURE:

Hardware:
Connections are made as per the circuit diagram.
Logic inputs are given as per the circuit diagram.
Observe the output and verify the truth table.

Simulation:

Write and draw the Digital logic system and write the Verilog code for above
system.
Enter the Verilog code in Xilinx software.
Check the syntax and simulate the above verilog code (using Xilinx) and
verify the output waveform as obtained.

THEORY:
The arithmetic logic unit (ALU) is a digital circuit that calculates arithmetic
operations (addition, subtraction, etc.) and logic operations (Exclusive OR, AND, OR
etc.) between two numbers. The ALU is a fundamental building block of the central
processing unit of a computer.
Many types of electronic circuits need to perform some type of arithmetic
operation, so even the circuit inside a digital watch will have a tiny ALU that keeps
adding 1 to the current time and keeps checking if it should beep timer etc.
ALU units typically need to be able to perform the basic logical operations
(AND, OR) including the addition operation. The inclusion of inverters on the inputs
enables the same ALU hardware to perform the subtraction operation (adding an
inverted operand) and
the operations NAND and NOR. A basic ALU design involves a collection of ALU
Slices, which each can perform the specified operation on a single bit. There is one
ALU slice for every bit in the operand.
The basic 2 bit ALU is designed using logic gates. The AND, OR, EX-OR gates
are used to perform the various operation such as OR, AND, XOR and addition. The
8:1Multiplexers are used to select between the various operations: OR, AND, XOR
and addition. All the operations are performed in parallel and the select signal (OP)
is used to determine which result to pass on to the rest of the data path. The carry
signal is only used for addition, is generated and passed out of the ALU for every
operation.


TRUTH TABLE:

Data Inputs: A and B

S1 S0 OPERATION
0 0 Sum of A & B
0 1 Carry of A& B
1 0
B A
1 1
B A




Verilog Coding:

module alu(y,a,b,s);
input a,b;
input [1:0]sel;
output reg z;
always@(sel,a,b)
begin
case(sel)
2b00: y=a^b;
2b01: y=a&b;
2'b10: y=~(a&b);
2'b11: y=(a|b);
default y=1bx;
endcase
end
endmodule








RESULT:

Thus the operation Arithmetic Logic Unit was verified using hardware and software
simulations


Ex.No.: MICROCONTROLLER BASED SYSTEMS DESIGN

AIM:
To design microcontroller based system for simple applications like security systems
combination lock etc. using 89c series flash micro controller.

APPARATUS REQUIRED:

1. 8051 microcontroller
2. Stepper Motor
3. Interface card

THEORY:

A motor in which the rotor is able to assume only discrete stationary angular position
is a stepper motor. They are used in printer, disk drive process control machine tools etc.
Two-phase stepper motor has two pairs of stator poles. Stepper motor windings A1, A2, B1,
B2 are cyclically excited with a DC current to run the motor in clockwise direction and
reverse phase sequence A1, B2, A2, B1 in anticlockwise stepping

Two-phase switching scheme:
In this scheme, any two adjacent stator windings are energized.



PROGRAMS:

MEMORY OPCODE LABEL NEMONICS
5000 90,45,00 Start MOV DPTR,#4500
5003 78,04 MOV RO,#04
5005 E0 L1 MOVX A,@DPTR
5006 C0,83 PUSH DPH
5008 C0,82 PUSH DPL
500A 90,FF,C0 MOV DPTR,#FFC0
500D 7A,FF MOV R2,#FF
500F 79,FF MOV R2,#FF
5011 7B,FE MOV R3,#FF
5013 DB,FE DJNZ R3,5013
5015 D9,FA DJNZ R1,5011
5017 OA,F6 DJNZ R2,500F
MEMORY OPCODE LABEL NEMONICS
5019 F0 MOVX@DPTR,A
501A D0,82 POP 82
501C D0,83 POP 83
501E A3 INC DPTR
501F D8,E4 DJNZ R0,5005
5021 80,FE SJMP 5021


MEMORY OPCODE LABEL NEMONICS
5550 90,46,00 Start MOV DPTR,#4600
5503 78,04 MOV RO,#04
5505 E0 L1 MOVX A,@DPTR
5506 C0,83 PUSH DPH
5508 C0,82 PUSH DPL
550A 90,FF,C0 MOV DPTR,#FFC0
550D 7A,FF MOV R2,#FF
550F 79,FF MOV R2,#FF
5511 7B,FE MOV R3,#FF
5513 DB,FE DJNZ R3,5513
5515 D9,FA DJNZ R1,5511
5517 OA,F6 DJNZ R2,550F
5519 F0 MOVX@DPTR,A
551A D0,82 POP 82
551C D0,83 POP 83
551E A3 INC DPTR
551F D8,E4 DJNZ R0,5505
5521 80,FE SJMP 5521


Inputs
4500 - 09
4501 - 05
4502 - 06
4503 - 0A

4600 - 0a
4601 - 06
4602 - 05
4603 - 09


RESULT:

Thus the operation Security system was verified using 8051 microcontroller.