module

csla16bit(a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,a15,b0,b1,b2,b3,b4,b5,b6,b7,b8,b
9,b10,b11,b12,b13,b14,b15,sel,s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,cout);
input
a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,a15,b0,b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11
,b12,b13,b14,b15,sel;
output s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,cout;
wire w1
group1 g1(a0,b0,a1,b1,s0,s1,w1);
group2 g2(a2,a3,b2,b3,w1,s2,s3,w2);
group3 g3(a4,a5,a6,b4,b5,b6,w2,s4,s5,s6,w3);
group4 g4(a7,a8,a9,a10,b7,b8,b9,b10,w3,s7,s8,s9,s10,w4);
group5 g5(a11,a12,a13,a14,a15,b11,b12,b13,b14,b15,w4,s11,s12,s13,s14,s15,cout);

endmodule

module group1(a0,b0,a1,b1,sum0,sum1,cout);
input a0,a1,b0,b1;
output sum0,sum1,cout;
wire w1,w2,w3,w4;
assign sum0=a0^b0;
assign w1=a0&b0;
assign w2=a1^b1;
assign w3=w1&w2;
assign w4=a1&b1;
assign cout=w3|w4;
assign sum1=w1^w2;
endmodule

module group2(a0,a1,b0,b1,sel,sum0,sum1,cout);
input a0,a1,b0,b1,sel;
output sum0,sum1,cout;
wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13;
assign w1=a0^b0;
assign w2=~w1;
assign w3=a0&b0;
assign w4=a0|b0;
assign w5=a1^b1;
assign w6=~w5;
mux_2 m1(w5,w6,w3,w7);
assign w8=w3&w5;
assign w9=a1&b1;
assign w10=w8|w9;
mux_2 m2(w5,w6,w4,w11);
assign w12=w5&w4;
assign w13=w12|w9;
mux_2 m3(w1,w2,sel,sum0);
mux_2 m4(w7,w11,sel,sum1);
mux_2 m5(w10,w13,sel,cout);
endmodule

module group3(a0,a1,a2,b0,b1,b2,sel,sum0,sum1,sum2,cout);
input a0,a1,a2,b0,b1,b2,sel;
output sum0,sum1,sum2,cout;
wire
w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14,w15,w16,w17,w18,w19,w20,w21,w22;
assign w1=a0^b0;
assign w2=~w1;
mux_2 m1(w1,w2,sel,sum0);
assign w3=a0&b0;
assign w4=a1^b1;
assign w5=~w4;
mux_2 m2(w5,w4,w3,w6);
assign w7=w3&w4;
assign w8=a1&b1;
assign w9=w7|w8;
assign w10=a0|b0;
mux_2 m3(w4,w5,w10,w11);
mux_2 m4(w6,w11,sel,sum1);
assign w12=w5&w10;
assign w13=w12|w8;

assign w14=a2^b2;
assign w15=~w14;
mux_2 m5(w14,w15,w9,w16);

assign w17=w14&w9;
assign w18=a2&b2;
assign w19=w17|w18;
mux_2 m6(w15,w16,w13,w20);
mux_2 m7(w16,w20,sel,sum2);
assign w21=w14&w13;
assign w22=w21|w18;

mux_2 m8(w22,w19,sel,cout);
endmodule

module group4(a0,a1,a2,a3,b0,b1,b2,b3,sel,sum0,sum1,sum2,sum3,cout);
input a0,a1,a2,a3,b0,b1,b2,b3,sel;
output sum0,sum1,sum2,sum3,cout;
wire
w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14,w15,w16,w17,w18,w19,w20,w21,w22,
w23,w24,w25,w26,w27,w28,w29,w30,w31;
assign w1=a0^b0;
assign w2=~w1;
mux_2 m1(w1,w2,sel,sum0);
assign w3=a0&b0;
assign w4=a1^b1;
assign w5=~w4;
mux_2 m2(w5,w4,w3,w6);
assign w7=w3&w4;
assign w8=a1&b1;
assign w9=w7|w8;
assign w10=a0|b0;
mux_2 m3(w4,w5,w10,w11);
mux_2 m4(w6,w11,sel,sum1);
assign w12=w5&w10;
assign w13=w12|w8;

assign w14=a2^b2;
assign w15=~w14;
mux_2 m5(w14,w15,w9,w16);

assign w17=w14&w9;
assign w18=a2&b2;
assign w19=w17|w18;
mux_2 m6(w15,w16,w13,w20);
mux_2 m7(w16,w20,sel,sum2);
assign w21=w14&w13;
assign w22=w21|w18;

assign w23=a3^b3;
assign w24=~w23;
mux_2 m8(w23,w24,w19,w25);
assign w26=w23&w19;
assign w27=a3&b3;
assign w28=w26|w27;
mux_2 m9(w24,w25,w22,w29);
mux_2 m10(w25,w29,sel,sum3);
assign w30=w23&w22;
assign w31=w30|w28;

mux_2 m11(w31,w28,sel,cout);

endmodule

module group5(a0,a1,a2,a3,a4,b0,b1,b2,b3,b4,sel,sum0,sum1,sum2,sum3,sum4,cout);
input a0,a1,a2,a3,a4,b0,b1,b2,b3,b4,sel;
output sum0,sum1,sum2,sum3,sum4,cout;
wire
w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14,w15,w16,w17,w18,w19,w20,w21,w22,
w23,w24,w25,w26,w27,w28,w29,w30,w31;
assign w1=a0^b0;
assign w2=~w1;
mux_2 m1(w1,w2,sel,sum0);
assign w3=a0&b0;
assign w4=a1^b1;
assign w5=~w4;
mux_2 m2(w5,w4,w3,w6);
assign w7=w3&w4;
assign w8=a1&b1;
assign w9=w7|w8;
assign w10=a0|b0;
mux_2 m3(w4,w5,w10,w11);
mux_2 m4(w6,w11,sel,sum1);
assign w12=w5&w10;
assign w13=w12|w8;

assign w14=a2^b2;
assign w15=~w14;
mux_2 m5(w14,w15,w9,w16);

assign w17=w14&w9;
assign w18=a2&b2;
assign w19=w17|w18;
mux_2 m6(w15,w16,w13,w20);
mux_2 m7(w16,w20,sel,sum2);
assign w21=w14&w13;
assign w22=w21|w18;

assign w23=a3^b3;
assign w24=~w23;
mux_2 m8(w23,w24,w19,w25);
assign w26=w23&w19;
assign w27=a3&b3;
assign w28=w26|w27;
mux_2 m9(w24,w25,w22,w29);
mux_2 m10(w25,w29,sel,sum3);
assign w30=w23&w22;
assign w31=w30|w28;

assign w32=a4^b4;
assign w33=~w32;
mux_2 m11(w32,w33,w28,w34);
assign w35=w32&w33;

assign w36=a4&b4;
assign w37=w35|w36;
mux_2 m12(w33,w34,w31,w38);
mux_2 m13(w34,w38,sel,sum4);
assign w39=w32&w31;
assign w40=w39|w37;

mux_2 m14(w40,w37,sel,cout);

endmodule