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ATMEGA32

ATMEGA32

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Published by api-19831863

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Published by: api-19831863 on Nov 30, 2009
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03/18/2014

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1
Features
\ue000High-performance, Low-power AVR\u00ae 8-bit Microcontroller
\u2022Advanced RISC Architecture

\u2013 131 Powerful Instructions \u2013 Most Single-clock Cycle Execution
\u2013 32 x 8 General Purpose Working Registers
\u2013 Fully Static Operation
\u2013 Up to 16 MIPS Throughput at 16 MHz
\u2013 On-chip 2-cycle Multiplier

\u2022Nonvolatile Program and Data Memories
\u2013 32K Bytes of In-System Self-Programmable Flash
Endurance: 10,000 Write/Erase Cycles

\u2013 Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation

\u2013 1024 Bytes EEPROM

Endurance: 100,000 Write/Erase Cycles
\u2013 2K Byte Internal SRAM
\u2013 Programming Lock for Software Security

\u2022JTAG (IEEE std. 1149.1 Compliant) Interface

\u2013 Boundary-scan Capabilities According to the JTAG Standard
\u2013 Extensive On-chip Debug Support
\u2013 Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

\u2022Peripheral Features
\u2013 Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
\u2013 One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode
\u2013 Real Time Counter with Separate Oscillator
\u2013 Four PWM Channels
\u2013 8-channel, 10-bit ADC

8 Single-ended Channels
7 Differential Channels in TQFP Package Only

2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
\u2013 Byte-oriented Two-wire Serial Interface
\u2013 Programmable Serial USART
\u2013 Master/Slave SPI Serial Interface
\u2013 Programmable Watchdog Timer with Separate On-chip Oscillator
\u2013 On-chip Analog Comparator

\u2022Special Microcontroller Features

\u2013 Power-on Reset and Programmable Brown-out Detection
\u2013 Internal Calibrated RC Oscillator
\u2013 External and Internal Interrupt Sources
\u2013 Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby

and Extended Standby
\u2022I/O and Packages
\u2013 32 Programmable I/O Lines
\u2013 40-pin PDIP, 44-lead TQFP, and 44-pad MLF
\u2022Operating Voltages
\u2013 2.7 - 5.5V for ATmega32L
\u2013 4.5 - 5.5V for ATmega32
\u2022Speed Grades
\u2013 0 - 8 MHz for ATmega32L
\u2013 0 - 16 MHz for ATmega32
\u2022Power Consumption at 1 MHz, 3V, 25\u00b0C for ATmega32L

\u2013 Active: 1.1 mA
\u2013 Idle Mode: 0.35 mA
\u2013 Power-down Mode: < 1 \u00b5A

8-bit
Microcontroller
with 32K Bytes
In-System
Programmable
Flash

ATmega32
ATmega32L
Preliminary
Rev. 2503D\u2013AVR\u201302/03
2
ATmega32(L)
2503D\u2013AVR\u201302/03
Pin Configurations
Figure 1.Pinouts ATmega32
Disclaimer

Typical values contained in this data sheet are based on simulations and characteriza- tion of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.

(XCK/T0) PB0
(T1) PB1
(INT2/AIN0) PB2
(OC0/AIN1) PB3
(SS) PB4
(MOSI) PB5
(MISO) PB6
(SCK) PB7

RESET
VCC
GND

XTAL2
XTAL1

(RXD) PD0
(TXD) PD1
(INT0) PD2
(INT1) PD3
(OC1B) PD4
(OC1A) PD5
(ICP) PD6

PA0 (ADC0) PA1 (ADC1) PA2 (ADC2) PA3 (ADC3) PA4 (ADC4) PA5 (ADC5) PA6 (ADC6) PA7 (ADC7) AREF

GND
AVCC

PC7 (TOSC2)
PC6 (TOSC1)
PC5 (TDI)
PC4 (TDO)
PC3 (TMS)
PC2 (TCK)
PC1 (SDA)
PC0 (SCL)
PD7 (OC2)

PA4 (ADC4) PA5 (ADC5) PA6 (ADC6) PA7 (ADC7) AREF

GND
AVCC

PC7 (TOSC2)
PC6 (TOSC1)
PC5 (TDI)
PC4 (TDO)

(MOSI) PB5
(MISO) PB6
(SCK) PB7

RESET
VCC
GND

XTAL2
XTAL1

(RXD) PD0
(TXD) PD1
(INT0) PD2

(INT1)PD3
(OC1B)PD4
(OC1A)PD5
(ICP)PD6
(OC2)PD7
VCC
GND
(SCL)PC0
(SDA)PC1
(TCK)PC2
(TMS)PC3
PB4(SS)
PB3(AIN1/OC
0)
PB2(AIN0/IN
T2)
PB1(T1)
PB0(XCK/T0)
GND
VCC
PA0(ADC0)
PA1(ADC1)
PA2(ADC2)
PA3(ADC3)
PDIP
TQFP/MLF
3
ATmega32(L)
2503D\u2013AVR\u201302/03
Overview

The ATmega32 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega32 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

Block Diagram
Figure 2.Block Diagram
INTERNAL
OSCILLATOR
OSCILLATOR
WATCHDOG
TIMER
MCU CTRL.
& TIMING
OSCILLATOR
TIMERS/
COUNTERS
INTERRUPT
UNIT
STACK
POINTER
EEPROM
SRAM
STATUS
REGISTER
USART
PROGRAM
COUNTER
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
PROGRAMMING
LOGIC
SPI
ADC
INTERFACE
COMP.
INTERFACE
PORTA DRIVERS/BUFFERS
PORTA DIGITAL INTERFACE

GENERAL
PURPOSE
REGISTERS

X
YZ
ALU
+-
PORTC DRIVERS/BUFFERS
PORTC DIGITAL INTERFACE
PORTB DIGITAL INTERFACE
PORTB DRIVERS/BUFFERS
PORTD DIGITAL INTERFACE
PORTD DRIVERS/BUFFERS
XTAL1
XTAL2
RESET
CONTROL
LINES
VCC
GND
MUX &
ADC
AREF
PA0 - PA7
PC0 - PC7
PD0 - PD7
PB0 - PB7
AVR CPU
TWI
AVCC

INTERNAL
CALIBRATED
OSCILLATOR

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