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Vhdl Code for Serial in Serial Out Shift Register Using Behavioral Modelling

Vhdl Code for Serial in Serial Out Shift Register Using Behavioral Modelling

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Published by meaow88
siso
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Published by: meaow88 on Nov 30, 2009
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05/28/2013

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VHDL CODE FOR SERIAL IN SERIAL OUT SHIFT REGISTER USINGBEHAVIORAL MODELLING
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity siso isPort ( sin,clk,rst : in STD_LOGIC;q: inout std_logic_vector(2 downto 0);sout : out STD_LOGIC);end siso;architecture Behavioral of siso isCOMPONENT DFFPORT (data,clock,rst:in std_logic;output:out std_logic);end component;begind0: dff port map(sin,clk,rst,q(0));d1: dff port map(q(0),clk,rst,q(1));d2: dff port map(q(1),clk,rst,q(2));d3: dff port map(q(2),clk,rst,sout);end Behavioral;
 
(a)(b)
FIG4.2 RTL SCHEMATIC FOR SERIAL IN SERIAL OUT SHIFT REGISTER USINGBEHAVIORAL MODELLING

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Divya Dawar added this note
its structural model not behavioral....
1 thousand reads
1 hundred reads
Payal Verma liked this
Anushree Saran liked this
Pratibha Singh added this note
its a structural model how can this program simulate?
srisridivine liked this
Pradeev Balakrishnan added this note
shift register

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