U.S. patent 6356122: Clock synthesizer with programmable input-output phase relationship. Granted to Sevalia et. al. on 2002-03-12 (filed None). Currently involved in at least 4 patent litigations: PLL Technologies Inc. v. Altera Corporation (Delaware);PLL Technologies Inc. v. Microsemi Corporation (Delaware);PLL Technologies Inc. v. Texas Instruments Incorporated (Delaware);PLL Technologies Inc. (Delaware). See http://news.priorsmart.com for more info.
Original Title
Clock synthesizer with programmable input-output phase relationship (US patent 6356122)
U.S. patent 6356122: Clock synthesizer with programmable input-output phase relationship. Granted to Sevalia et. al. on 2002-03-12 (filed None). Currently involved in at least 4 patent litigations: PLL Technologies Inc. v. Altera Corporation (Delaware);PLL Technologies Inc. v. Microsemi Corporation (Delaware);PLL Technologies Inc. v. Texas Instruments Incorporated (Delaware);PLL Technologies Inc. (Delaware). See http://news.priorsmart.com for more info.
U.S. patent 6356122: Clock synthesizer with programmable input-output phase relationship. Granted to Sevalia et. al. on 2002-03-12 (filed None). Currently involved in at least 4 patent litigations: PLL Technologies Inc. v. Altera Corporation (Delaware);PLL Technologies Inc. v. Microsemi Corporation (Delaware);PLL Technologies Inc. v. Texas Instruments Incorporated (Delaware);PLL Technologies Inc. (Delaware). See http://news.priorsmart.com for more info.