ABSTRACT

Weather Monitoring Systems are the systems, which continuously watch the
changes in the weather by continuous gathering of the present weather conditions.
Weather The continuous weather condition is sensed by a sensor and transmitted through
modem.

Weather Monitoring System (WMS) interface between the real world of physical
parameters, which are analog, and the artificial world of digital computation and control.
Digital systems are used widely because complex circuits are low cost, accurate, and
relatively simple to implement. In addition there is rapid growth in the use of
microcomputers to perform difficult digital control and measurement functions. Modem
works as a Weather acquisition device.

A modem is a device or program that enables a computer to transmit data over,

for example, telephone or cable lines. Computer information is stored digitally, whereas
information transmitted over telephone lines is in the form of analog waves. A modem
converts between these two forms. Modem transmission conforms to the standards set by
ITU-Telecommunications with the V-series Recommendation.

This Project finds it application in real time for Weather Monitoring. Weather
Monitoring System (WMS) is used to retrieve data like temperature, pressure and
Voltage, Currents to remote host. The SHT11 is supplied in a surface-mountable LCC
(Leadless Chip Carrier) type package. The sensors housing consists of a Liquid Crystal
Polymer (LCP) cap with epoxy glob top on a standard 0.8mm FR4 substrate. The device
is free of lead, Cd and Hg.

This project mainly deals with acquisition of temperature and Humidity by using
temperature and Humidity sensor (SHT11) interfaced with Micro controller. The
peripherals equipped here are micro controller, Temperature and humidity sensor, LCD
Display interface, AtoD Converter, Modem along with Power supply unit.
INTERFACES USED:

POWER SUPPLY:

The power supply unit is used to provide a constant 5V supply to different IC’s
this is a standard circuits using external 12VDC adapter and fixed 3-pin voltage regulator.
Diode is added in series to avoid Reverse voltage.

MICRO CONTROLLER:

The 89C51 is a low cost Micro controller from either ATMEL or

PHILIPS. It has a 40-pin configuration and other components are interfaced to its ports.
The entire functionality of the Digital Data Acquisition System device is under the
control of Micro controller. The Micro controller takes input from the external sources
and routes them to the appropriate devices as programmed in it.

TEMPERATURE AND HUMIDITY SENSOR:

SHT11 is a sensor, which gives temperature and humidity at a place. SHT11 is a

single chip relative humidity and temperature multi sensor module comprising a
calibrated output. The two wire serial interface and internal voltage regulation allows
easy and fast system integration. Its tiny size and low power consumption makes it the
ultimate choice for even the most demanding applications.

LCD DISPLAY:

Generation of LCD supply voltage (external supply The PCD8544 is a low power
CMOS LCD controller/driver, designed to drive a graphic display of 48 rows and84
columns. All necessary functions for the display are provided in a single chip, including
on-chip generation of LCD supply and bias voltages, resulting in a minimum of external
components and low power consumption.

MODEM:

The Z02215 is a synchronous single –chip V.22bis modem capable of 2400 bps
full duplex over dial-up lines. It is a full-featured, self-controlled modem that includes a
modem controller, DSP, and Analog Front End (AFE) functions. This device is
specifically designed for use in embedded modem applications where space,
performance, and low power consumption are key requirements.

The bellow figure shows the Weather Monitoring System. It mainly consists of

• Micro Controller
• LCD Module
• RTC Module
• Humidity and Temperature
• Zilog Modem
 BLOCK DIAGRAM:

PC

48x84 matrix LCD Display Interface

PCD 8554
48X84 Matrix LCD

Real Time Atmel/Phillip

Clock
PCF 8563 Micro Controller
89C51 PSTN Line
 SHT11
Sensirion
ADC Modem
MC145041 Z02215

89C51 MICROCONTROLLER

INTRODUCTION OF MICROCONTROLLER:

BASIC MICROCONTROLLER BLOCK DIAGRAM:

There are three busses involved in accessing memory:

Address bus
Data bus
 Control bus

READ CYCLE:
1. CPU places address on address bus.
2. Control signals memory - address on address bus is valid
3. Memory chip fetches data from location specified by the address and places on the
data bus
4. Control signals CPU - data on data bus is valid
5. CPU takes data from data bus

WRITE CYCLE:

1. CPU places address on address bus

2. Control signals memory - address on address bus is valid.
3. CPU places data on the data bus
4. Control signals memory - data on data bus is valid
5. Memory chip takes data from data bus and places it in the Location specified by the
address

BASIC DIFFERENCE BETWEEN MICROPROCESSOR AND MICROCONTROLLER:

A microprocessor system consists of a microprocessor with memory, input ports

and output ports connected to it externally. A microcontroller is a single chip containing a
microprocessor, memory, input ports and output ports. Since all four blocks reside on the
one chip, a microcontroller is much faster than a microprocessor system

MEMORY:

we can split memory into two types;

 RAM and ROM RAM stands for random access memory. The are two features of
RAM which distinguish it from ROM. RAM is read/write - data can be written to
and read from RAM. RAM is volatile - data is lost once the power to a RAM chip is lost.

Random access refers to the fact that data from any location in the memory chip is
accessible at any time (you simply put the desired address on the address bus). ROM
stands for read only memory. As with RAM, it is random access but it differs from RAM
in two ways:

ROM, as the name suggests, is read only. You cannot write to a ROM chip. A
ROM chip must be programmed, but once programmed, it cannot be (easily) changed
ROM is non-volatile - when power is removed from the chip data is not lost.

There are many types of ROM available; PROM, EPROM, EEPROM and Flash
are the most common.

MICRO CONTROLLER 89C51:

The 8051 is just one of the MCS-51 family of microcontrollers developed by

intel. The design of each of the MCS-51 microcontrollers are more or less the same. The
differences between each member of the family is the amount of on-chip memory and the
number of timers.

Phillips 89C51 contains a non-volatile FLASH program memory that is parallel

programmable. Phillips 89C51, 8-bit Micro controller from MHS-51 Intel family, with
4K bytes of flash and 128 bytes of internal RAM had been used. It has a 40-pin
configuration and other components of interfaced to its ports. The Micro controller takes
input from the external sources and routes them to the appropriate devices as
programmed in it.

FEATURES:
89C51 Central Processing Unit
On-chip FLASH Program Memory
Speedup to 33 MHz
Fully Static Operation
RAM expandable externally up to 64 Kbytes
Four interrupt priority levels
Six interrupt sources
Four 8-bit input output ports
Full-duplex enhanced UART
-Framing error detection
-Automatic address recognition
Three 16-bit timers/counters T0, T1and additional T2
Programmable clock out
Second DPTR register
Asynchronous port reset
Power control modes
-Clock can be stopped and resumed
-Idle mode
-Power down mode
Low EMI
Wakeup from power down by an external interrupt
non-volatile FLASH program memory that is parallel programmable
Flash memory features
FLASH EPROM internal program memory with chip erases.
Up to 64K byte external program memory if the internal program memory is disabled
Programmable security bits.
10,000 minimum erase/program cycles for each byte
8051 MICRO CONTROLLER ARCHITECTURE:
1.DESCRIPTION OF BLOCK DIAGRAM:
CPU:

BLOCK DIAGRAM OF CPU:

The microcontroller consists of eight bit Arithmetic Logic Unit (ALU),

Associated Register Array means registers like register A, register B, PSW (program
status word), SP (stack pointer), and a 16-bit PC (program counter) and a 16-bit DPTR
(data pointer) register

ALU:

The ALU performs arithmetic and logic functions on 8-bit variables. The ALU
can perform addition, subtraction, multiplication and division and the logic unit can
perform logical operations. An important and unique feature of the microcontroller
architecture is that the ALU can also manipulate 1 bit as well as 8-bit data types.
Individual bits may be set, cleared, complemented, moved, tested and used in logic
computation.

ACCUMULATOR:
 The Accumulator, as its name suggests, is used as a general register to accumulate
the results of a large number of instructions. It can hold an 8-bit (1-byte) value and is the
most versatile register, the microcontroller has due to the shear number of instructions
that make use of the accumulator. Accumulator holds a source of operand and stores the
result of the arithmetic operations such as addition, subtraction, multiplication and
division. The accumulator can be the source or destination register for logical operations.
The accumulator has several exclusive functions such as rotate, parity computation;
testing for 0, sign acceptor etc. and so on.

PROGRAM COUNTER:

The program counter points to the address of the next instruction to be executed.
As the CPU fetches the opcode from the program ROM, the program counter is
implemented to point to the next instruction. The Microcontroller can access program
addresses 0000 to FFFFH, a total of 64K bytes of code.

When the 8051 is initialized PC always starts at 0000h and is incremented each
time an instruction is executed. PC is always incremented by one. Since some
instructions require 2 or 3 bytes the PC will be incremented by 2 or 3 in these cases. The
Program Counter is special in that there is no way to directly modify its value.

TYPES OF MEMORY:

The 8051 has three very general types of memory. To effectively program the
8051 it is necessary to have a basic understanding of these memory types.
The memory types are illustrated in the following diagram They are:
1.On-Chip Memory
2.External Code Memory
EXTERNAL RAM:
 On-Chip Memory refers to any memory (Code, RAM, or other) that physically
exists on the microcontroller itself. On-chip memory can be of several types, but we'll get
into that shortly.

External Code Memory is code (or program) memory that resides off-chip. This is
often in the form of an external EPROM.

External RAM is RAM memory that resides off-chip. This is often in the form of
standard static RAM or flash RAM.

CODE MEMORY:

Code memory is the memory that holds the actual 8051 program that is to be run.
This memory is limited to 64K and comes in many shapes and sizes. Code memory may
be found on-chip, either burned into the microcontroller as ROM or EPROM. Code may
also be stored completely off-chip in an external ROM or, more commonly, an external
EPROM. Flash RAM is also another popular method of storing a program. Various
combinations of these memory types may also be used--that is to say, it is possible to
have 4K of code memory on-chip and 64k of code memory off-chip in an EPROM.

When the program is stored on-chip the 64K maximum is often reduced to 4k, 8k,
or 16k. This varies depending on the version of the chip that is being used. Each version
offers specific capabilities and one of the distinguishing factors from chip to chip is how
much ROM/EPROM space the chip has.

However, code memory is most commonly implemented as off-chip EPROM.

This is especially true in low-cost development systems and in systems developed by
students.

EXTERNAL RAM:

As an obvious opposite of Internal RAM, the 8051 also supports what is called
External RAM.

External RAM is any random access memory which is found off-chip. Since the
memory is off-chip it is not as flexible in terms of accessing, and is also slower. For
example, to increment an Internal RAM location by 1 requires only 1 instruction and 1
instruction cycle. To increment a 1-byte value stored in External RAM requires 4
instructions and 7 instruction cycles. In this case, external memory is 7 times slower!
What External RAM loses in speed and flexibility it gains in quantity. While Internal
RAM is limited to 128 bytes (256 bytes with an 8052), the 8051 supports External RAM
up to 64K.

ON-CHIP MEMORY:

The 8051 includes a certain amount of on-chip memory. On-chip memory is

really one of two types: Internal RAM and Special Function Register (SFR) memory. The
layout of the 8051's internal memory is presented in the following memory map:
 As is illustrated in this map, the 8051 has a bank of 128 bytes of Internal RAM.
This Internal RAM is found on-chip on the 8051 so it is the fastest RAM available, and it
is also the most flexible in terms of reading, writing, and modifying its contents. Internal
RAM is volatile, so when the 8051 is reset this memory is cleared.

The 128 bytes of internal ram is subdivided as shown on the memory map. The
first 8 bytes (00h - 07h) are "register bank 0". By manipulating certain SFRs, a program
may choose to use register banks 1, 2, or 3. These alternative register banks are located in
internal RAM in addresses 08h through 1Fh. We'll discuss "register banks" more in a
later chapter. For now it is sufficient to know that they "live" and are part of internal
RAM.

Bit Memory also lives and is part of internal RAM. We'll talk more about bit
memory very shortly, but for now just keep in mind that bit memory actually resides in
internal RAM, from addresses 20h through 2Fh.

The 80 bytes remaining of Internal RAM, from addresses 30h through 7Fh, may
be used by user variables that need to be accessed frequently or at high-speed. This area
is also utilized by the microcontroller as a storage area for the operating stack. This fact
severely limits the 8051s stack since, as illustrated in the memory map, the area reserved
for the stack is only 80 bytes--and usually it is less since this 80 bytes has to be shared
between the stack and user variables.

REGISTER BANKS:

The 8051 uses 8 "R" registers which are used in many of its instructions. These
"R" registers are numbered from 0 through 7 (R0, R1, R2, R3, R4, R5, R6, and R7).
These registers are generally used to assist in manipulating values and moving data from
one memory location to another however, as the memory map shows, the "R" Register
R4 is really part of Internal RAM. The microcontroller has four distinct register banks.
When the 8051 is first booted up, register bank 0 (addresses 00h through 07h) is used by
default. The register banks really reside in the first 32 bytes of Internal RAM.

BIT MEMORY:

The 8051 being a communications-oriented microcontroller, gives the user the

ability to access a number of bit variables. These variables may be either 1 or 0. There
are 128 bit variables available to the user, numbered 00h through 7Fh. The user may
make use of these variables with commands such as SETB and CLR. It is important to
note that Bit Memory is really a part of Internal RAM. In fact, the 128 bit variables
occupy the 16 bytes of Internal RAM from 20h through 2Fh. Bit memory is not really a
new type of memory. Its really just a subset of Internal RAM. But since the 8051
provides special instructions to access these 16 bytes of memory on a bit by bit basis it is
useful to think of it as a separate type of memory. it is just a subset of Internal RAM--and
that operations performed on Internal RAM can change the values of the bit variables.

SPECIAL FUNCTION REGISTER (SFR) MEMORY:

Special Function Registers (SFRs) are areas of memory that control specific
functionality of the 8051 processor. For example, four SFRs permit access to the 8051s
32 input/output lines. Another SFR allows a program to read or write to the 8051s serial
port. Other SFRs allow the user to set the serial baud rate, control and access timers, and
configure the 8051s interrupt system. program may inspect and/or change the operating
mode of the 8051 by manipulating the values of the 8051's Special Function Registers.
The SFR is part of Internal Memory.

The program may inspect and/or change the operating mode of the 8051 by
manipulating the values of the 8051's Special Function Registers. SFRs are accessed as if
they were normal Internal RAM. The only difference is that Internal RAM is from
address 00h through 7Fh whereas SFR registers exist in the address range of 80h through
FFh Each SFR has an address (80h through FFh) and a name.

THE DIAGRAM OF THE SFR:

Although the address range of 80h through FFh offer 128 possible addresses,
there are only 21 SFRs in a standard 8051. All other addresses in the SFR range (80h
through FFh) are considered invalid. Writing to or reading from these registers may
produce undefined values or behavior.

SFR TYPES:

As mentioned in the chart itself, the SFRs that have a blue background are SFRs
related to the I/O ports. The 8051 has four I/O ports of 8 bits, for a total of 32 I/O lines.
Whether a given I/O line is high or low and the value read from the line are controlled by
the SFRs in green.

The SFRs with yellow background are SFRs which in some way control the
operation or the configuration of some aspect of the 8051. For example, TCON controls
the timers, SCON controls the serial port.

The remaining SFRs, with green backgrounds, are "other SFRs." These SFRs can
be thought of as auxiliary SFRs in the sense that they don't directly configure the 8051
but obviously the 8051 cannot operate without them. For example, once the serial port
has been configured using SCON, the program may read or write to the serial port using
the SBUF register.

SFR DESCRIPTIONS:

P0 (Port 0, Address 80h, Bit-Addressable): This is input/output port 0. Each bit of

this SFR corresponds to one of the pins on the microcontroller. For example, bit 0 of port
0 is pin P0.0, bit 7 is pin P0.7. Writing a value of 1 to a bit of this SFR will send a high
level on the corresponding I/O pin whereas a value of 0 will bring it to a low level.
SP (Stack Pointer, Address 81h): This is the stack pointer of the microcontroller. This
SFR indicates where the next value to be taken from the stack will be read from in
Internal RAM. If you push a value onto the stack, the value will be written to the address
of SP + 1. That is to say, if SP holds the value 07h, a PUSH instruction will push the
value onto the stack at address 08h. This SFR is modified by all instructions which
modify the stack, such as PUSH, POP, LCALL, RET, RETI, and whenever interrupts are
provoked by the microcontroller.

DPL/DPH (Data Pointer Low/High, Addresses 82h/83h):

The SFRs DPL and DPH work together to represent a 16-bit value called the
Data Pointer. The data pointer is used in operations regarding external RAM and some
instructions involving code memory. Since it is an unsigned two-byte integer value, it can
represent values from 0000h to FFFFh (0 through 65,535 decimal).

PCON (Power Control, Addresses 87h): The Power Control SFR is used to
control the 8051's power control modes. Certain operation modes of the 8051 allow the
8051 to go into a type of "sleep" mode which requires much less power. These modes of
operation are controlled through PCON. Additionally, one of the bits in PCON is used to
double the effective baud rate of the 8051's serial port.

TCON (Timer Control, Addresses 88h, Bit-Addressable):

The Timer Control SFR is used to configure and modify the way in which the
8051's two timers operate. This SFR controls whether each of the two timers is running
or stopped and contains a flag to indicate that each timer has overflowed. Additionally,
some non-timer related bits are located in the TCON SFR. These bits are used to
configure the way in which the external interrupts are activated and also contain the
external interrupt flags which are set when an external interrupt has occured.

TMOD (Timer Mode, Addresses 89h):

The Timer Mode SFR is used to configure the mode of operation of each of the
two timers. Using this SFR your program may configure each timer to be a 16-bit timer,
an 8-bit autoreload timer, a 13-bit timer, or two separate timers. Additionally, you may
configure the timers to only count when an external pin is activated or to count "events"
that are indicated on an external pin.

TIMER 0 AND TIMER 1:

The "timer” or "counter "function is selected by control bits C/T in the special
function register TMOD. These two timer/counters have for operating modes, which are
selected by bit-pairs (M1/M0) in TMOD. Modes 0, 1, and 2 are the same for both
timers/counters. Mode 3 is different.

TL0/TH0 (Timer 0 Low/High, Addresses 8Ah/8Ch):

These two SFRs, taken together, represent timer 0. Their exact behavior depends
on how the timer is configured in the TMOD SFR; however, these timers always count
up. What is configurable is how and when they increment in value.

GATE: When set, start and stop of timer by hardware

When reset, start and stop of timer by software

C/T : Cleared for timer operation

Set for counter operation

M1 M0 MODE OPERATING MODE

0 0 0 13-bit timer mode

 0 1 1 16-bit timer mode

1 0 2 8-bit auto reload mode

1 1 3 Split timer mode

TL1/TH1 (Timer 1 Low/High, Addresses 8Bh/8Dh):

These two SFRs, taken together, represent timer 1. Their exact behavior depends
on how the timer is configured in the TMOD SFR; however, these timers always count
up. What is configurable is how and when they increment in value.
Address =88H.
Bit addressable.

TF: Timer overflow flag: Set by hardware when the timer/counter overflows. It is
cleared by hardware, as the processor vectors to the interrupt service routine.
TR: timer run control bit: Set or cleared by software to turn timer or counter on/off.
IE: set by CPU when the external interrupt edge (H-to-L transition) is detected. It is
cleared by CPU when the interrupt is processed.
IT: set/cleared by software to specify falling edge/low-level triggered external
interrupt.

P1 (Port 1, Address 90h, Bit-Addressable):

This is input/output port 1. Each bit of this SFR corresponds to one of the pins on
the microcontroller. For example, bit 0 of port 1 is pin P1.0, bit 7 is pin P1.7. Writing a
value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas
a value of 0 will bring it to a low level.
SCON (Serial Control, Addresses 98h, Bit-Addressable):

The Serial Control SFR is used to configure the behavior of the 8051's on-board
serial port. This SFR controls the baud rate of the serial port, whether the serial port is
activated to receive data, and also contains flags that are set when a byte is successfully
sent or received.
Bit addressable.

8H
REN set or cleared by software to enable or disable reception.
TB 8 not widely used.
RB 8 not widely used.
TI transmits interrupt flag. Set by hardware at the beginning of the stop bit in mode
1. It must be cleared by software.
RI received interrupts flag. Set by hardware halfway through the stop bit time in
mode 1. It must be cleared by software.

SM0 SM1 Serial mode 0

0 0 Synchronous mode
0 1 8-bit data, 1 start bit, 1 stop bit, variable
baud rate
1 0 9- bit data, 1 start bit, 1 stop bit, fixed
baud rate
1 1 9- bit data, 1 start bit, 1 stop bit, variable
baud rate

SBUF (Serial Control, Addresses 99h):

The Serial Buffer SFR is used to send and receive data via the on-board serial
port. Any value written to SBUF will be sent out the serial port's TXD pin. Likewise, any
value which the 8051 receives via the serial port's RXD pin will be delivered to the user
program via SBUF. In other words, SBUF serves as the output port when written to and
as an input port when read from.

P2 (Port 2, Address A0h, Bit-Addressable):

This is input/output port 2. Each bit of this SFR corresponds to one of the pins on
the microcontroller. For example, bit 0 of port 2 is pin P2.0, bit 7 is pin P2.7. Writing a
value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas
a value of 0 will bring it to a low level.
IE (Interrupt Enable, Addresses A8h):

A single microcontroller can serve several devices. In the interrupt method,

whenever any device needs its service, the device notifies the microcontroller by sending
it an interrupt signal. Upon receiving an interrupt signal, the microcontroller interrupts
whatever it is doing and serves the device. The program associated with the interrupt is
called the interrupt service routine (ISR). The advantageous of interrupts is that the
microcontroller can serve many devices based on the priority assigned to it.

SIX INTERRUPTS IN THE 89C51:

1. Reset.
2. Two interrupts are set aside for the timers.
3. Two interrupts are set aside for hardware external hardware interrupts.
4. Serial Communications has a single interrupt (receive and transfer).
The Interrupt Enable SFR is used to enable and disable specific interrupts. The low 7 bits
of the SFR are used to enable/disable the specific interrupts, where as the highest bit is
used to enable or disable ALL interrupts. Thus, if the high bit of IE is 0 all interrupts are
disabled regardless of whether an individual interrupt is enabled by setting a lower bit.
EA disable all interrupts. If EA = 0, now interrupt is acknowledged. If EA = 1, each
interrupt source is individually enabled or disabled by setting or clearing its enable a lap
bit.
---- Not implemented, reserved for future use.
ET2 enables or disables timer 2 overflow or capturer interrupt.
ES enables or disables the serial port interrupt.
ET1 enables or disables timer 1 overflow interrupt.
EX1 enables or disables external interrupt 1.
ET0 enables or disables timer 0 overflow interrupt.
EX0 enables or disables external interrupt 0.

P3 (Port 3, Address B0h, Bit-Addressable):

This is input/output port 3. Each bit of this SFR corresponds to one of the pins on
the microcontroller. For example, bit 0 of port 3 is pin P3.0, bit 7 is pin P3.7. Writing a
value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas
a value of 0 will bring it to a low level.

IP (Interrupt Priority, Addresses B8h, Bit-Addressable):

The Interrupt Priority SFR is used to specify the relative priority of each
interrupt. On the 8051, an interrupt may either be of low (0) priority or high (1) priority.
An interrupt may only interrupt interrupts of lower priority. For example, if we configure
the 8051 so that all interrupts are of low priority except the serial interrupt, the serial
interrupt will always be able to interrupt the system, even if another interrupt is currently
executing. However, if a serial interrupt is executing no other interrupt will be able to
interrupt the serial interrupt routine since the serial interrupt routine has the highest
priority.

--- IP.7 Reserved

--- IP.6 Reserved
PT2 IP.5 Timer2 Interrupt Priority bit (for 8052 only)
PS IP.4 Serial Port Interrupt Priority Bit
PT1 IP.3 Timer1 Interrupt Priority Bit
PX1 IP.2 External Interrupt Priority Bit
PT0 IP.1 Timer0 Interrupt Priority Bit
PX0 IP.0 External Interrupt Priority Bit

PSW (Program Status Word, Addresses D0h, Bit-Addressable):

The Program Status Word is used to store a number of important bits that are set
and cleared by microcontroller instructions. The PSW SFR contains the carry flag, the
auxiliary carry flag, the overflow flag, and the parity flag. Additionally, the PSW register
contains the register bank select flags which are used to select which of the "R" register
banks are currently selected.

PSW (program status word) register:

The program status word (PSW) register is on 8-bit register. It is also referred to as the
flag register.
CY Carry-flag.
AC Auxiliary carry-flag.
---- Available to the user for general-purpose.
RS1 register bank selector bit 1.
RS0 register bank selector bit 0.
OV overflow flag.
---- User definable bit.
P Parity flag. Set/cleared by hardware each instruction cycle to indicate an
odd/even member of 1 bit in the accumulator.

Other SFRs:

The chart above is a summary of all the SFRs that exist in a standard 8051. All
derivative microcontrollers of the 8051 must support these basic SFRs in order to
maintain compatibility with the underlying MSCS51 standard.
1–8: (Port 1):

Each of these pins can be used as either input or output according to your needs.
Also, pins 1 and 2 (P1.0 and P1.1) have special functions associated with Timer.

9: RESET SIGNAL:

High logical state on this input halts the MCU and clears all the registers.
Bringing this pin back to logical state zero starts the program anew as if the power had
just been turned on. In another words, positive voltage impulse on this pin resets the
MCU. Depending on the device's purpose and environs, this pin is usually connected to
the push-button, reset-upon-start circuit or a brown out reset circuit (covered in the
previous chapter). The image shows one simple circuit for safe reset upon starting the
controller. It is utilized in situations when power fails to reach its optimal voltage.

10-17:

Port 3 as with Port 1, each of these pins can be used as universal input or output.
However, each pin of Port 3 has an alternative function.
Beside its role as universal I/O port, each pin of Port 3 has an alternate function. In order
to use one of these functions, the pin in question has to be designated as input, i.e. the
appropriate bit of register P3 needs to be set. From a hardware standpoint, Port 3 is
similar to Port 0.

As can be seen from the individual descriptions of the ports, they all share highly
similar structure. However, you need to consider which task should be assigned to which
port. For example: if utilizing port as output with high level (5V), avoid using Port 0, as
its pins cannot produce high logical level without an additional resistor connected to +5V.
If using other port to a same end, bear in mind that built-in resistors have
relatively high values, producing the currents limited to few hundreds of amperes as pin
output.

Pin 10:

RXD - serial input for asynchronous communication or serial output for

synchronous communication.

Pin 11:

TXD - serial output for asynchronous communication or clock output for

synchronous communication

Pin 12: INT0 - input for interrupt 0

Pin 13: INT1 - input for interrupt 1
Pin 14: T0 - clock input of counter 0
Pin 15: T1 - clock input of counter 1
Pin 16: WR - signal for writing to external (add-on) RAM memory
Pin 17: RD - signal for reading from external RAM memory.
18-19: X2 and X1;

Input and output of internal oscillator. Quartz crystal controlling the frequency
commonly connects to these pins. Capacitances within the oscillator mechanism (see the
image) are not critical and are normally about 30pF. Instead of a quartz crystal, miniature
ceramic resonators can be used for dictating the pace. In that case, manufacturers
recommend using somewhat higher capacitances (about 47 puffs). New Mucus works at
frequencies from 0Hz to 50MHz+.

20: GND: Ground

21- 28:

Port 2 if external memory is not present, pins of Port 2 act as universal

input/output. If external memory is present, this is the location of the higher address byte,
i.e. addresses A8 – A15. It is important to note that in cases when not all the 8 bits are
used for addressing the memory (i.e. memory is smaller than 64kB), the rest of the
unused bits are not available as input/output.

When external memory is used, this port contains the higher address byte
(addresses A8–A15), similar to Port 0. Otherwise, it can be used as universal I/O port.
29: PSEN; MCU activates this bit (brings to low state) upon each reading of byte
(instruction) from program memory. If external ROM is used for storing the program,
PSEN is directly connected to its control pins.

Of the external memory, MCU sends the lower byte of the address register
(addresses A0 – A7) to port P0 and activates the output ALE. External register
(74HCT373 or 74HCT375 circuits are common), memorizes the state of port P0 upon
receiving a signal from ALE pin, and uses it as part of the address for memory chip.
During the second part of the mechanical MCU cycle, signal on ALE is off, and port P0
is used as Data Bus. In this way, by adding only one cheap integrated circuit, data from
port can be multiplexed and the port simultaneously used for transferring both addresses
and data.

31: EA:

Bringing this pin to the logical state zero (mass) designates the ports P2 and P3
for transferring addresses regardless of the presence of the internal memory. This means
that even if there is a program loaded in the MCU it will not be executed, but the one
from the external ROM will be used instead. Conversely, bringing the pin to the high
logical state causes the controller to use both memories, first the internal, and then the
external (if present).
32-39:

Port 0 Similar to Port 2, Port 0 has two-fold role if external memory is used, it
contains the lower address byte (addresses A0-A7); otherwise all bits of the port are
either input or output. Another feature of this port comes to play when it has been
designated as output. Unlike other ports, Port 0 lacks the "pull up" resistor (resistor with
+5V on one end). This seemingly insignificant change has the following consequences:
When designated as input, pin of Port 0 acts as high impedance offering the infinite input
resistance with no "inner" voltage.

When designated as output, pin acts as "open drain". Clearing a port bit grounds
the appropriate pin on the case (0V). Setting a port bit makes the pin act as high
impedance. Therefore, to get positive logic (5V) at output, external "pull up" resistor
needs to be added for connecting the pin to the positive pole.
Therefore, to get one (5V) on the output, external "pull up" resistor needs to be added for
connecting the pin to the positive pole.

40: VCC: Power +5V.

SERIAL COMMUNICATION:

When a microprocessor communicates with the outside world, it provides data in

byte-sized chunks. In some cases, such as printers, the information is simply grabbed
from the 8-bit data bus and presented to the 8-bit data bus of the printer. This can work
only if the cable is not too long, since long cables diminish and ever distort signals.
Furthermore, and 8-bit data path is expensive. For these reasons, serial communication is
used for transferring data between two systems located at distances of hundreds of feet to
millions of miles apart.

The fact that in serial communication a single data line is used instead of the 8-bit
data line of parallel communication makes it not only much cheaper but also makes it
possible for two computers located in two different cities to communicate over the
telephone.

Serial data communication uses two methods, a synchronous and asynchronous.

The synchronous method transfers a block of data at a time while the synchronous
transfers a single byte at a time. It is mean possible to write software to use either of
these methods, but the programs can be tedious and long. For this reason, there are
special IC chips made by many manufacturers for serial data communications. These
chips are commonly referred to as UART (universal asynchronous receiver-transmitter)
and USART (universal synchronous -asynchronous receiver-transmitter). The8051 chips
has built-in UART, which is discussed

ASYNCHRONOUS SERIAL COMMUNICATION AND DATA FRAMING:

Transmitter and receiver do not explicitly coordinate each data transmission.

Transmitter can wait arbitrarily long between transmissions. Used, for example, when
transmitter such as a keyboard may not always have data ready to send Asynchronous
may also mean no explicit information about where data bits begin and end The data
coming in at the receiving end of the data line in a serial data transfer is all 0's and 1's; it
is difficult to make sense of the data unless the sender and receiver agree on a set of rules,
a protocol, on how the data is packed, how many bits constitute the character, and when
the data begins and ends.

START AND STOP BITS:

A synchronous serial data communication is widely used for character orientation

transmissions. In the asynchronous method, each character is placed in between start and
stop bits. This is the called framing. In data framing for asynchronous communications,
the data, such as ASCII characters, are packed in between a start bit and a stop bits. The
start bit is always one-bit but the stop bit can be one or two bits. If the transmitter and
receiver are using different speeds, stop bit will not be received at the expected time
problem is called framing error. The start bit is always a 0 and the stop bit is 1.

PARITY BIT:

In some systems in order to maintain data integrity, the parity bit of the character
byte is included in the data frame. This means that for each character we have a single
parity bit in addition to start and stop bits. The parity bit is odd or even. In case of an
odd parity bit the number of data bits of a book of including the parity bit, is even.

DATA TRANSFER RATE:

The rate of data transfer in serial data communication is stated in bps (bits per
second). Another widely used terminology for bps is baud rate. Baud rate is defined as
the number of signal changes per second. As far as the conductor wire is concerned, the
baud rates as bps are the same. If each signal change represents more than one bit, bits
per second may be greater than baud rate.

RS232 STANDARDS:

Two allow compatibility among the data communication equipment made by

various manufacturers; an interfacing standard called RS232, was set by the electronics
industries association (EIA) in 1960. RS 232 is the standard defined for the connection
of "Data Terminal Equipment" (DTE) to "Data Communications Equipment" (DCE).

DTE (Data Terminal Equipment) is a generic term for an item which forms part of
the "information processing" portions of a system. Examples are: computer, printer, and
terminal.

DCE (Data Communications Equipment) is a device, which provides an interface

between a DTE and a communications link.
INTERFACE FOR DTE/DCE CONNECTION:

All Signals Are “Ground Referenced” to in Pin 7

TXD, RXD---- Transmit and Receive Signal
RTS---- Request to Send, from DTE
CTS---- Clear to send, from DCE together with RTS
DTE---- Data Terminal Ready, indicates to the modem that a DTE is Connected and
enabled.
DSR--- Data Set Ready, indicates to the DTE that the modem is present and turned on
CD-- Carrier Detect, indicates that this modem is receiving a signal from the remote
modem.

In RS 232, a 1 is represented by -3 to -25V which is called Mark, while a 0 bit is

+ 3 to + 25V which is called Space. To connect any RS 232 to a µc system, voltage
converters such as Max 232are used. Max 232 IC chips are commonly referred to as line
drivers.8.3. MAX 232. The RS 232 is not compatible with micro controllers, so a line
driver converts the RS 232's signals to TTL voltage levels.
RS 232 WIRING AND CONNECTORS:

RS-232 Defines Serial, Asynchronous communication, Serial bits are encoded

and transmitted one at a time. Asynchronous characters can be sent at any time and bits
are not individually synchronized. This is standard for transfer of characters across
copper wire.

FLOW CONTROL AND HARDWARE HANDSHAKING:

RTS/CTS: These signals are often now used to throttle the rate at which data is
delivered between a DTE and modem: the DTE "drops" RTS when its buffers are nearly
full, and the modem does the same using the CTS signal. This is nowadays referred to as
"hardware handshaking".

It's worth noting that modern high-speed modems almost universally use the
RTS/CTS pair for this purpose. In fact, without hardware handshaking, data compression
in modems would not be possible.

DTR/DSR and CD:

These signals are occasionally used in a similar way to RTS/CTS, particularly

between computers and printers.
 TESTING

PORT TESTING:

TO TEST THE 89C51 SYSTEM AND ITS PORTS:

Test the operation of the ports of your 89C51 trainer as follows. Assemble and
run the test program below. The test program toggles the ports of the 89C51. Use a logic
probe or the LED of your digital trainer to watch the bits of the ports toggle on and off.
The time delay in between the "on" and "off" states is 1 second

/*program to test 89C51 ports*/

org 00h
mov a,#55h
route: mov p0,a
mov p1,a
mov p2,a
call delay1sec
cpl a
jmp route
delay1sec: mov r3,#10
again: mov r4,#200
back: mov r5,#250
same: djnz r5, same
djnz r4,back
djnz r3,again
ret
end
IMPLEMENTATION:
 BASIC FORM OF ALP
BASIC FORM OF ASSEMBLY LANGUAGE PROGRAM:
 Now that the basic form of an assembly language program has been given, the
next question is: how it is created, assembled and made ready to run? The steps to create
an executable assembly language program are outlined as follows.
1. First we use an editor to type in a program similar to program. Many excellent editors
or word processors are available that can be used to create and/or edit the program. A
widely used editor is the MS-DOS EDIT program (or notepad in Windows), which comes
with all Microsoft operating systems. Notice that the editor must be able to produce an
ASCII file. For many assemblers, the file names follow the usual DOS conventions, but
the source file has the extension "ASM "or "SRC ", depending on which assembler you
are using. Check your assembler for the convention. The "asm ", extension for the
source file is used by an assembler in the next step.

2. The "ASM "source file containing the program code is created in step 1 is fed to
an 8051 assembler. The assembler converts the instructions into machine code. The
assembler will produce an object file and a list file. The extension for the object file is
"OBJ "by the extension for the list file is "1ST ".
3. Assemblers require a third step calling linking. The link program takes one or more
objects files and produces an absolute object file with the extension "ABS". 8051
trainers that have a monitor program use this ABS file.

4. Next the "ABS "file is fed into a program called "OH "(Object to Hex Converter)
which creates a file with extension "HEX "that these ready to burn into ROM. This
program comes with all 8051 assemblers. Recent Windows-based assemblers combine
steps 2 through 4 into one step.

EVALUATION OF KEIL SOFTWARE:

1. Start the µVision Program

2. After the program has started:
Select File, New… from the program menu
 Type your assembly file. The following is an example of a toggle program.

org 0H
mov A, #0ffH
route:
mov P1, A
acall delay1msec
cpl a
mov P2, a
acall delay1msec
sjmp route

delay1msec:
mov R3, #200
up: mov R2, #250
same: djnz R2, same
djnz R3, up
ret
end

3. Select File, Save… from the program menu

The first time you save the program a dialog box will popup and allow you to name
your file and file type.
Save program with filename: xxxxx.asm
The File type is mentioned at last (.asm) means assembly language
4. Select Project, New Project… from the program menu
Give some project name: xxxx.prj
5. Click on the Add button
A dialog-box appears, allowing you to add files to the project
Change the file type to Assembly.
6. Select your assembly file.
Click on the Add button then close the Add dialog box.
7. Click on Save in your Project dialog box.
8. Select Project, Make: Build Project from the program menu
 This creates the HEX file you need for the 8051

Using the Keil dScope Debugger

1. Select Run, dScope debugger… from the program menu

The debug program will start a new session
2. Select File, load CPU driver from the program menu
Choose the 8051.dll from the drop down list box; you can also select this directly.
3. Select File, load object file from the program menu.
Change the file type to HEX
Select your hex file, e.g. Toggle. Hex
Click OK
4. You should now see the source code of the file typed in earlier
5. Select Peripherals, I/O Ports from the program menu. so that you can see the how
output varies on ports.
Select Port 0, Port 1, Port 2 and Port 3
6. Click on go to see the real time update of the I/O ports.
7. Click on stop when you are finished.
You can also single step through you program or set break points at locations that you
want the debugger to stop at. To set a breakpoint, double click on the line.
 GRAPHICAL LCD

FEATURES:

• Single chip LCD controller/driver

• 48 row, 84 column outputs
• Display data RAM 48  8 4 bits
• On-chip:
• Generation of LCD supply voltage (external supply also possible)
• Generation of intermediate LCD bias voltages
• Oscillator requires no external components (external clock also possible).
• External RES (reset) input pin
• Serial interface maximum 4.0 Mbits/s
• CMOS compatible inputs
• Mux rate: 48
• Logic supply voltage range VDD to VSS: 2.7 to 3.3 V
• Display supply voltage range VLCD to VSS
• 6.0 to 8.5 V with LCD voltage internally generated (voltage generator enabled)
• 6.0 to 9.0 V with LCD voltage externally supplied (voltage generator switched-
off).
• Low power consumption, suitable for battery operated systems
• Temperature compensation of VLCD
• Temperature range: 25 to +70 o C.

GENERAL DESCRIPTION:

The PCD8544 is a low power CMOS LCD controller/driver, designed to drive a

graphic display of 48 rows and 84 columns. All necessary functions for the display are
provided in a single chip, including on-chip generation of LCD supply and bias voltages,
resulting in a minimum of external components and low power consumption. The
PCD8544 interfaces to microcontrollers through a serial bus interface. The PCD8544 is
manufactured in n-well CMOS technology.

APPLICATIONS:
Telecommunications equipment.

BLOCK DIAGRAM:

FUNCTIONAL DESCRIPTION:
OSCILLATOR:

The on-chip oscillator provides the clock signal for the display system. No
external components are required and the OSC input must be connected to VDD. An
external clock signal, if used, is connected to this input.
ADDRESS COUNTER (AC):

The address counter assigns addresses to the display data RAM for writing. The
X-address X6 to X0 and the Y-address Y2 to Y0 are set separately. After a write
operation, the address counter is automatically incremented by 1, according to the V flag.

DISPLAY DATA RAM (DDRAM):

The DDRAM is a 48 ´ 84 bit static RAM which stores the display data. The RAM
is divided into six banks of 84 bytes (6 ´ 8 ´ 84 bits). During RAM access, data is
transferred to the RAM through the serial interface. There is a direct correspondence
between the X-address and the column output number.

TIMING GENERATOR:

The timing generator produces the various signals required to drive the internal
circuits. Internal chip operation is not affected by operations on the data buses.

DISPLAY ADDRESS COUNTER:

The display is generated by continuously shifting rows of RAM data to the dot
matrix LCD through the column outputs. The display status (all dots on/off and
normal/inverse video) is set by bits E and D in the ‘display control’ command.
LCD ROW AND COLUMN DRIVERS:

The PCD8544 contains 48 row and 84 column drivers, which connect the
appropriate LCD bias voltages in sequence to the display in accordance with the data to
be displayed. Figure 2 shows typical waveforms. Unused outputs should be left
unconnected.
PIN CONFIGURATION:

1. R0 TO R47 ROW DRIVER OUTPUTS:

These pads output the row signals.

2. C0 TO C83 COLUMN DRIVER OUTPUTS:

These pads output the column signals.

3. VSS1, VSS2: NEGATIVE POWER SUPPLY RAILS:

Supply rails VSS1 and VSS2 must be connected together.

4. VDD1, VDD2: POSITIVE POWER SUPPLY RAILS:

Supply rails VDD1 and VDD2 must be connected together.

5. VLCD1, VLCD2: LCD POWER SUPPLY:

 Positive power supply for the liquid crystal display. Supply rails VLCD1 and
VLCD2 must be connected together.

6. T1, T2, T3 AND T4: TEST PADS:

T1, T3 and T4 must be connected to VSS, T2 is to be left open. Not accessible to
user.

7. SDIN: SERIAL DATA LINE:

Input for the data line.

8. SCLK: SERIAL CLOCK LINE:

Input for the clock signal: 0.0 to 4.0 Mbits/s.

9. D/C: MODE SELECT:

Input to select either command/address or data input.

10. SCE: CHIP ENABLE:

The enable pin allows data to be clocked in. The signal is active LOW.

11. OSC: OSCILLATOR:

When the on-chip oscillator is used, this input must be connected to VDD. An
external clock signal, if used, is connected to this input. If the oscillator and external
clock are both inhibited by connecting the OSC pin to VSS, the display is not clocked
and may be left in a DC state. To avoid this, the chip should always be put into Power-
down mode before stopping the clock.

12 RES: RESET:
This signal will reset the device and must be applied to properly initialize the
chip. The signal is active LOW.
Fig: DDRam to display mapping
ADDRESSING:

Data is downloaded in bytes into the 48 by 84 bits RAM data display matrix of
PCD8544, as indicated in Figs. 3, 4, 5 and 6. The columns are addressed by the address
pointer. The address ranges are: X 0 to 83 (1010011), Y 0 to 5 (101). Addresses outside
these ranges are not allowed. In the vertical addressing mode (V = 1), the Y address
increments after each byte (see Fig.5). After the last Y address (Y = 5), Y wraps around
to 0 and X increments to address the next column. In the horizontal addressing mode (V
= 0), the X address increments after each byte (see Fig.6). After the last X address (X =
83), X wraps around to 0 and Y increments to address the next row. After the very last
address (X = 83 and Y = 5), the address pointers wrap around to address (X = 0 and Y =
0).

DATA STRUCTURE:
handbook, full

Fig:RAM format, addressing.

Fig: Sequence of writing data bytes into RAM with vertical addressing (V = 1).
48 X 84 PIXELS MATRIX LCD CONTROLLER/DRIVER:

Fig: Sequence of writing data bytes into RAM with horizontal addressing (V = 0).

TEMPERATURE COMPENSATION:

Due to the temperature dependency of the liquid crystals’ viscosity, the LCD
controlling voltage VLCD must be increased at lower temperatures to maintain optimum
contrast. Figure 7 shows VLCD for high multiplex rates. In the PCD8544, the
temperature coefficient of VLCD, can be selected from four values (see Table 2) by
setting bits TC1 and TC0.

1. Upper Limit.
2. Typical curve
3. Temperature coefficient of IC

4. Lower limit
INSTRUCTIONS:

The instruction format is divided into two modes: If D/C (mode select) is set
LOW, the current byte is interpreted as command byte (see Table 1). Figure 8 shows an
example of a serial data stream for initializing the chip. If D/C is set HIGH, the following
bytes are stored in the display data RAM. After every data byte, the address counter is
incremented automatically.

The level of the D/C signal is read during the last bit of data byte. Each
instruction can be sent in any order to the PCD8544. The MSB of a byte is transmitted
first. Figure 9 shows one possible command stream, used to set up the LCD driver. The
serial interface is initialized when SCE is HIGH. In this state, SCLK clock pulses have no
effect and no power is consumed by the serial interface. A negative edge on SCE enables
the serial interface and indicates the start of a data transmission.

Fig.General format of data stream.

Fig:Serial data stream, example.

TIMING DIAGRAM SHOW THE SERIAL BUS PROTOCOL:

• When SCE is HIGH, SCLK clock signals are ignored; during the HIGH time of
SCE, the serial interface is initialized (see Fig.12).

• SDIN is sampled at the positive edge of SCLK.

• D/C indicates whether the byte is a command (D/C = 0) or RAM data (D/C = 1);
it is read with the eighth SCLK pulse.

• If SCE stays LOW after the last bit of a command/data byte, the serial interface
expects bit 7 of the next byte at the next positive edge of SCLK (see Fig.12).

• A reset pulse with RES interrupts the transmission. No data is written into the
RAM.

The registers are cleared. If SCE is LOW after the positive edge of RES, the serial
interface is ready to receive bit 7 of a command/data byte (see Fig.13).
Instruction Set:
INITIALIZATION:

Immediately following power-on, the contents of all internal registers and of the
RAM are undefined. A RES pulse must be applied. Attention should be paid to the
possibility that the device may be damaged if not properly reset.

All internal registers are reset by applying an external RES pulse (active LOW) at
pad 31, within the specified time. However, the RAM contents are still undefined. The
RES input must be £0.3VDD when VDD reaches VDDmin (or higher) within a
maximum time of 100 ms after VDD goes HIGH
RESET FUNCTION:

After reset, the LCD driver has the following state:

• Power-down mode (bit PD = 1)
• Horizontal addressing (bit V = 0) normal instruction set (bit H = 0)
• Display blank (bit E = D = 0)
• Address counter X6 to X0 = 0; Y2 to Y0 = 0
• Temperature control mode (TC1 TC0 = 0)
• Bias system (BS2 to BS0 = 0)
• VLCD is equal to 0, the HV generator is switched off (VOP6 to VOP0 = 0)
• After power-on, the RAM contents are undefined.

FUNCTION SET:

BIT PD:
• All LCD outputs at VSS (display off)
• Bias generator and VLCD generator off, VLCD can be disconnected
• Oscillator off (external clock possible)
• Serial bus, command, etc. function
 • Before entering Power-down mode, the RAM needs to be filled with ‘0’s to
ensure the specified current consumption.

BIT V:

When V = 0, the horizontal addressing is selected. The data is written into the
DDRAM as shown in Fig.

When V = 1, the vertical addressing is selected. The data is written into the
DDRAM, as shown in Fig.

BIT H:

When H = 0 the commands ‘display control’, ‘set Y address’ and ‘set X address’
can be performed; when H = 1, the others can be executed. The ‘write data’ and ‘function
set’ commands can be executed in both cases.

DISPLAY CONTROL:
Bits D and E:

Bits D and E select the display mode (see Table 2).

SET Y ADDRESS OF RAM:

Yn defines the Y vector addressing of the display RAM.

 Table 3:Y vector addressing

Set X address of RAM:

The X address points to the columns. The range of X is 0 to 83 (53H).

TEMPERATURE CONTROL:

The temperature coefficient of VLCD is selected by bits TC1 and TC0.

BIAS VALUE:

The bias voltage levels are set in the ratio of R - R - nR - R - R, giving a 1/(n + 4)
bias system. Different multiplex rates require different factors n (see Table 4). This is
programmed by BS2 to BS0. For Mux 1 : 48, the optimum bias value n, resulting in 1/8
bias, is given by:
SET VOP VALUE:

The operation voltage VLCD can be set by software. The values are dependent
on the liquid crystal selected. VLCD = a + (VOP6 to VOP0) b [V]. In the PCD8544,
a = 3.06 and b = .06 giving a program range of 3.00 to 10.68 at room temperature.

Note: That the charge pump is turned off if VOP6 to VOP0 is set to zero.
For Mux 1 : 48, the optimum operation voltage of the liquid can be calculated as:

where Vth is the threshold voltage of the liquid crystal material used.
 Caution,
as VOP
increases with
lower
temperatures,
care must be
taken not to set
a VOP that will exceed the maximum of 8.5 V when operating at -25 °C.

APPLICATION INFORMATION:
 REAL TIME CLOCK

A real-time clock (RTC) is a computer clock (most often in the form of an

integrated circuit chip) that keeps track of the current time even when the computer is
turned off. It is used in many kinds of computers, and is present in all modern personal
computers. RTCs are also present in many embedded systems some models of integrated
Real-time clock circuits are the DS1307 from Maxim and the PCF8563 from Phillips.

Real-time clocks run on a special battery that is not connected to the normal
power supply. In contrast, clocks that are not real-time do not function when the
computer is off. RTC should not be confused with real-time computing. It also shouldn't
be confused with CPU clock (The CPU clock regulates the execution of instructions.).

Block Diagram:
FEATURES:

 Operating voltage: 2.0V~5.5V

 Two data transmission modes: single-byte,
 Maximum input serial clock: 500kHz at or burst mode
 Serial I/O transmission
 Operating current: less than 400nA at 2V,
 All registers store BCD format
 HT1380: 8-pin DIP package

PIN ASSIGNMENT:

The HT1380/HT1381 is a serial timekeeper IC that provides seconds, minutes,

hours, day, date, month and year information. The number of days in each month and
leap years are automatically adjusted. The HT1380/HT1381 is designed for low power
consumption and can operate in two modes:

• One is the 12-hour mode with an AM/PM indicator.

• The other is the 24-hour mode.

The HT1380/HT1381 has several registers to store the corresponding information

with 8-bitdata formats. A 32768Hz crystal is required to provide the correct timing. In
order to minimize the pin number, the HT1380/HT1381 use a serial I/O transmission
method to interface with a microprocessor.
 Only three wires are required: (1) REST, (2) SCLK and (3) I/O. Data can be
delivered 1 byte at a time or in a burst of up to 8 bytes.

For each data transfer, a Command Byte is initiated to specify which register is
accessed. This is to determine whether a read, write, or test cycle is operated and whether
a single byte or burst mode transfer is to occur. Refer to the table shown below and
follow the steps to write the data to the chip. First give a Command Byte of
HT1380/HT1381, and then write a data in the register.

This table illustrates the correlation between Command Byte and their bits:
CH: Clock Halt bit
CH=0 oscillator enabled
CH=1 oscillator disabled

WP: Write protect bit

WP=0 register data can be written in
WP=1 register data can not be written in

Bit 7 of Reg2:
12/24 mode flag
Bit 7=1, 12-hour mode
Bit 7=0, 24-hour mode
Bit 5 of Reg2:

AM/PM mode defined

AP=1 PM mode
AP=0 AM mode

R/W signal :

The LSB of the Command Byte determines whether the data in the register be
read or be written to.

When it is set as 0 means that a write cycle is to take place otherwise this chip
will be set into the read mode.

A0~A2 :

A0 to A2 of the Command Byte is used to specify which registers are to be

accessed. There are eight registers used to control the month data, etc., and each of these
registers has to be set as a write cycle in the initial time.

Burst mode :

When the Command Byte is 10111110 (or 10111111), the HT1380/HT1381 is

configured in burst mode. In this mode the eight clock/calendar registers can be written
(or read) in series, starting with bit 0 of register address 0 (see the timing on the next
page).

Test mode :
 When the Command Byte is set as 1001xxx1, HT1380/HT1381 is configured in
test mode. Holtek uses the test mode only for testing purposes. If used generally,
unpredictable conditions may occur.

Write protect register :

This register is used to prevent a write operation to any other register. Data can be
written into the designated register only if the Write Protect signal (WP) is set to logic 0.
The Write Protect Register should be set first before restarting the system or before
writing the new data to the system, and it should set as logic1in the read cycle. The Write
Protect bit cannot be written to in the burst mode. Logic is turned on and the
address/command sequence can access the corresponding shift register. The REST pin is
also used to terminate either single-byte or burst mode data format.

Clock Halt bit :

D7 of the Seconds Register is defined as the Clock Halt Flag (CH). When this bit
is set to logic 1, the clock oscillator is stopped and the chip goes into a low-power
standby mode. When this bit is written to logic 0, the clock will start.

12-hour/24-hour mode :

The D7 of the hour register is defined as the 12-hour or 24-hour mode select bit.
When this bit is in high level, the 12-hour mode is selected otherwise it’s the 24-hour
mode.

AM-PM mode :
 These are two functions for the D5 of the hour register determined by the value
D7 of the same register. One is used in AM/PM selection on the 12-hour mode. When D5
is logic 1, it is PM, otherwise it is AM. The other is used to set the second 10-hour bit
(20~23 hours) on the 24-hour mode.

Reset and Serial Clock control :

The REST pin is used to allow access data to the shift register like a toggle
switch. When the REST pin is taken high, the built-in control Data in and Data out .

In writing a data byte with HT1380/HT1381, the read/write should first set as
R/W=0 in the Command Byte and follow with the corresponding data register on the
rising edge of the next eight SCLK cycles. Additional SCLK cycles are ignored. Data
inputs are entered starting with bit 0. In reading a data on the register of
HT1380/HT1381, R/W=1 should first be entered as input. The data bit outputs on the
falling edge of the next eight SCLK cycles. Note that the first data bit to be transmitted
on the first falling edge after the last bit of the read command byte is written. Additional
SCLK cycles re-transmit the data bytes as long as REST remains at high level. Data
outputs are read starting with bit 0.

Crystal selection :

A 32768Hz crystal can be directly connected to the HT1380/HT1381 via pin 2

and pin 3 (X1, X2). In order to obtain the correct frequency, two additional load
capacities (C1, C2) are needed. The value of the capacity depends on how accurate the
crystal is. The input signal of SCLK is a sequence of a falling edge followed by a rising
edge and it is used to synchronize the register data whether read or write. For data input,
the data must be read after the rising edge of SCLK. The data on the I/O pin becomes
output mode after the falling edge of the SCLK. All data transfer terminates if the REST
pin is low and the I/O pin goes to a high impedance state.
HUMIDITY AND TEMPERATURE SENSOR
SHT1x / SHT7x :(Humidity & Temperature Sensor )

Features:

• Relative humidity and temperature sensors

• Dew point
• Fully calibrated, digital output
• Excellent long-term stability
• No external components required
• Ultra low power consumption
• Surface mountable or 4-pin fully interchangeable
• Small size
• Automatic power down

BLOCK DIAGRAM:
BLOCK DIAGRAM DESCRIPTION :

The SHTxx is a single chip relative humidity and temperature multi sensor
module comprising a calibrated digital output. The device includes a capacitive
polymer sensing element for relative humidity and a band gap temperature sensor.
Both are seamlessly coupled to a 14bit analog to digital converter and a serial interface
circuit on the same chip. This results in superior signal quality, a fast response time and
insensitivity to external disturbances (EMC) at a very competitive price.

Each SHTxx is individually calibrated in a precision humidity chamber with a

chilled mirror hygrometer as reference. The calibration coefficients are programmed
into the OTP memory. These coefficients are used internally during measurements
to calibrate the signals from the sensors. The 2-wire serial interface and internal
voltage regulation allows easy and fast system integration. Its tiny size and low power
consumption makes it the ultimate choice for even the most demanding applications.

The device is supplied in either a surface-mountable LCC (Leadless Chip

Carrier) or as a pluggable 4-pin single-in-line type package. Customer specific packaging
options may be available on request.
APPLICATIONS :

• HVAC
• Automotive
• Consumer Goods
• Weather Stations
• (De-) Humidifiers

INTERFACE SPECIFICATIONS :

Figure :Typical application circuit

Power Pins :

The SHTxx requires a voltage supply between 2.4V and 5.5V. After
powerup the device needs 11ms to reach its .sleep. state. No commands should be
sent before that time. Power supply pins (VDD, GND) may be decoupled with a
100 nF capacitor.

Serial Interface (Bidirectional 2-wire) :

 The serial interface of the SHTxx is optimized for sensor readout and power
consumption and is not compatible with I2C interfaces, see FAQ for details.

Serial clock input (SCK) :

The SCK is used to synchronize the communication between a microcontroller

and the SHT1x / SHT7x. Since the interface consists of fully static logic there is
no minimum SCK frequency.

Serial data (DATA):

The DATA tristate pin is used to transfer data in and out of the device. DATA
changes after the falling edge and is valid on the rising edge of the serial clock
SCK. During communication the DATA line must remain stable while SCK is high. To
avoid signal contention the microcontroler should only drive DATA low. An external
pull-up resistor (e.g 10k ) is required to pull the signal high. (See Figure ) Pull-up
resistors are often included in I/O circuits of microcontrollers.

SENDING A COMMAND :

To initiate a transmission, a .Transmission Start. sequence has to be issued. It

consists of a lowering of the DATA line while SCK is high, followed by a low pulse
on SCK and raising DATA again while SCK is still high.

Figure : "Transmission Start" sequence

 The subsequent command consists of three address bits (only .000. is
currently supported) and five command bits. The SHT1x/SHT7x indicates the
proper reception of a command by puling the DATA pin low (ACK bit) after the
falling edge of the 8th SCK clock. The DATA line is released (and goes high) after the
faling edge of the 9th SCK clock.

Measurement sequence (RH and T) :

After issuing a measurement command (.00000101. for RH, 00000011. for

Temperature) the controller has to wait for the measurement to complete. This takes
approximately 11/55/210ms for a 8/12/14bit measurement. The exact time varies by up to
15% with the speed of the internal oscilator. To signal the completion of a
measurement, the SHT1x pulls down the data line. The controller must wait for this
.data ready. signal before starting to toggle SCK again.

Two bytes of measurement data and one byte of CRC checksum will then be
transmitted. The uC must acknowledge each byte by pulling the DATA line low.
All values are MSB first, right justified. (e.g. the 5th SCK is MSB for a 12bit value, for a
8bit result the first byte is not used). Communication terminates after the acknowledge
bit of the CRC data. If CRC-8 checksum is not used the controller may terminate the
communication after the measurement data LSB by keeping ack high. The device
automaticaly returns to sleep mode after the measurement and communication have
ended.

Connection reset sequence :

If communication with the device is lost the following signal sequence wil reset
its serial interface:
 While leaving DATA high, toggle SCK 9 or more times. This must be followed
by a .Transmission Start. sequence preceding the next command. This sequence
resets the interface only. The status register preserves its content.

Fig: Connection Reset Sequence

CRC-8 Checksum calculation :

The whole digital transmission is secured by a 8 bit checksum. It ensures

that any wrong data can be detected and eliminated.
CONVERTING OUTPUT TO PHYSICAL VALUES :

Relative Humidity :

To compensate for the non-linearity of the humidity sensor and to obtain the
full accuracy it is recommended to convert the readout with the folowing formula1:

Table:Humidity conversion coefficients

TEMPERATURE :

The bandgap PTAT (Proportional To Absolute Temperature) temperature sensor

is very linear by design. Use the following formula to convert from digital readout
to temperature.

Table : Temperature conversion coefficients

 ZILOG MODEM(Z02215)

Features:

• Complete modem integrated circuit with integrated controller, data pump and
Analog Front End (AFE) with active hybrid
• Includes an AT command set interpreter in the on-chip ROM with no external
memory required.
• Programmable country parameters through AT commands or EEPROM interface
Automatic determination of AT command speed and parity.
• Includes V.14 asynchronous to synchronous conversion.
• Accepts asynchronous or synchronous terminal data
• Speed matching and RTS/CTS flow control between the modem and the terminal
• Voice answer detection
• Line-In-Use detection before connection
• Pick-up detection during connections
• Supports Tone or Pulse dialing
• Call progress monitoring controls
• Guard tone controls
• Line quality monitoring and auto-retrain
• Auto-Dial and Auto-Answer
• Supports telephone dial blacklisting
• Data modem throughput to 2400 bps
• ITU V.22bis, V.23, V.22, V.21
• Bell 212A, Bell 103, Bell 202, Bell 202T
• FSK (V.23 1200/75 bps, Bell 202/Bell 202T 1200/150 bps, V.21/Bell 103 300
bps), DPSK (V.22/Bell 212A 1200 bps), or QAM Encoding (V.22bis 2400 bps)
• V.23 with Minitel line reversal
• Programmable bi-quad call progress tone detectors.
• Adaptive equalization to compensate for a wide variety of line conditions.
• Programmable transmit attenuation and selectable receive threshold.

• Fully-programmable call progress detectors for precise call program monitoring,

including signal quality detectors, tone detectors, tone generators, and transmit
signal levels that aid in rapid country qualifications.
• On-chip peripheral, a full-duplex voice band AFE with 12-bit resolution
• Dynamic power management: power-saving SLEEP modes
• North American Type-I Caller ID
• 44-Pin PLCC, 44-Pin VQFP footprint
• Single +5 VDC power supply
• Minimal external logic
• 0_C to +70_C standard temperature range and –40_C to +85_C extended
temperature range.
General Description:

The Z02215 is a synchronous single-chip V.22bis modem capable of 2400 bps

full-duplex over dial-up lines. It is a full-featured, self-controlled modem that includes a
modem controller, DSP, and Analog Front End (AFE) functions. This device is
specifically designed for use in embedded modem applications where space,
performance, and low-power consumption are key requirements.

Operating over the Public Switched Telephone Network (PSTN), the Z02215
meets the modem standards for V.22bis, V.22, V.23 (Minitel), V.21, Bell 212A, Bell 202,
Bell 202T, and Bell 103. A typical modem can be created by simply adding a phone- line
interface (DAA), and DTE interface.

All modulation, demodulation, filtering, Analog to Digital (A/D), and Digital to

Analog (D/A) conversion functions for transmission and reception are provided onchip.
Automatic compromise equalizers are included to optimize performance over a wide
range of line types. The Z02215 device compensates for a wide variety of adverse line
conditions by using adaptive equalizers.
The Z02215 provides comprehensive selectable and programmable tone
generation and detection. Transmit drivers and receive amplifiers can be connected
directly to a Data Access Arrangement (DAA) by adding a transformer, or a silicon
DAA, reducing the external circuits to a minimum.

In addition, the Z02215 provides further system-level savings by providing built-

in filters for both the transmitter analog output and the receiver analog Input. This
configuration eliminates the need for external filtering components. The analog front end
of the Z02215 includes an active hybrid circuit that improves modem performance and
reduces system-level costs by reducing the requirement for external components.
 The Z02215 device operates on a single +5 VDC power supply. During periods of
no traffic, the modem can be placed into SLEEP mode, reducing power consumption
through Dynamic Power Management. All signals with an overline, are active Low. For
example, B/W, in which WORD is active Low; and B/W, in which BYTE is active Low.

BLOCK DIAGRAM:
PIN DESCRIPTION:

Figure :Z02215 44-Lead PLCC Pin Identification (for Prototype Only)

Figure:Z02215 44-Lead VQFP Pin Identification
SYSTEM INFORMATION:
Figure illustrates the system block diagram.

Fig:EM Inter connection with the PC and Telephone Line

Modem is inter connected to the PC and micro controller. MAX 232 converts the
RS232 signals into TTL level signals.

PARALLEL HOST INTERFACE:

With the Parallel Host Interface, a host controller can put the Z02215 on its
processor bus and access it as a peripheral. The Parallel Interface consists of two host
registers:

• Register 0–Parallel Interface Data Register (PIDR)

• Register 1–Parallel Interface Status Register (PISR)

PIDR is the data register for transmitting and receiving data, including the AT
commands.

In RECEIVE DATA mode (when HRD, HCS, HA0, S/P are Low), Z02215 reads
the data on the Host Parallel Data bus (HD0–HD7) for the external host to read the
contents.

In TRANSMIT DATA mode (when HWR, HCS, HA0, S/P are Low), Z02215
reads the contents placed on the Host Parallel Data bus (HD0–HD7) by the external host
processor.
 PISR is the Status register. Bits 0, 1, 6 and 7 of this register are defined in
hardware, and bits 2, 3, 4, and 5 are defined in software as follows:

STATUS REGISTER:

OPERATING MODES:
 The modem controller software features several different states of operation.

IDLE:

When the modem is in the IDLE state it is not communicating with another
modem. The modem accepts AT commands from the terminal while IDLE.

DIALING:

When the modem dials it performs the same tasks a person uses to dial a
telephone. The modem does not accept AT commands or data from the terminal while
dialing.

HANDSHAKE:

When the modem handshakes it communicates with another modem to determine

the data rate the two modems use to communicate. Handshaking takes place at the
beginning of each connection between two modems. The originator and answerer of a
connection perform different actions while handshaking. The modem does not accept AT
commands or pass data from the terminal while handshaking.
ON-LINE:

After successfully completing Handshaking the modems enter the ON-LINE state.
When a modem is in the ON-LINE state, data received from its terminal is sent over the
telephone line to the other modem. Data received from the other modem is sent to the
terminal.

COMMAND:

If the terminal sends a special escape sequence to a modem in the ON-LINE state,
the modem enters the COMMAND state. During COMMAND state the modem
maintains the connection with the other modem but does not pass data between the
terminal and the other modem. Instead, data received from the terminal is treated as AT
commands in the same way as if the modem was in the Idle state. The modem can be
returned to the ON-LINE state by the O command. Data received from the other modem
while a modem is in COMMAND state is discarded unless the modem can buffer it for
display on the terminal when the modem re-enters the ON-LINE state.

RETRAIN:

During a telephone line connection, the modem tries to remain synchronized with
the remote modem by adapting to changes in telephone line connection and bridging
transient noises such as call waiting, analog switching and cross talk. In V.22bis and
higher speed data modes, if the modem loses synchronization with the remote modem
data can not be received until synchronization is restored by a process called Retraining.
During Retraining the modem accepts data and commands from the terminal but does not
transmit data to, or receive data from, the other modem.
AT COMMAND SET:

Command lines are typed to the modem from the terminal when the modem is in
the IDLE or COMMAND state. The modem does not execute any of the commands in a
command line until after the command line is ended by the end-of-line character <CR>.
A command line is a string of characters starting with the A and T characters and ending
with a special end-of-line character, <CR>. Characters typed before the AT are ignored.
Command lines contain, at most, 40 characters after the AT. The modem does not
execute any of the commands in a command line that is too long. To echo command line
characters, use the E1 command.

Typing mistakes can be aborted by using a special BackSpace character, <BS>,

after the initial A and T characters are entered.

A partial command line can be aborted by typing a Ctrl-X character. The modem
returns an OK result code and ignores the partial AT command line.

Command lines may contain several commands one after another. The Answer
(A), Dial (D), and Go ON-LINE (O) commands usually cause the following commands
in the command line to be ignored.

COMMAND LINE EXECUTION:

The characters in a command line are executed one at a time. Any unexpected
characters (except control characters) stop command line execution and return an
ERROR result code. Unexpected characters include numbers outside the range of values
accepted by the command. All control characters in a command line except Ctrl-X (and
the special characters such as <CR> and <BS>) are ignored. The numerical argument of
a command is assumed to be 0 if it is not provided. For example, the commands
ATH<CR> and ATH0<CR> both hang up the telephone line. When the modem has
executed a command line, the result code of the most recent command executed is
returned to the terminal. If the value written to a modem S-register is outside the range of
values accepted by the S-register, then its value is set to the nearest allowed value.
Leading 0s in numeric arguments, including S-register numbers, are ignored. For
example, both set S-register S1 to 2:

ATS1=2
ATS01=2

All numeric arguments, including S-register numbers, are decimal (base 10).

AT COMMAND PREFIX:

Each modem command line begins with the letters A and T. The modem uses
these characters to determine the data rate and parity from the terminal.

A/ REPEAT LAST COMMAND:

To repeat the commands in the most recent command line, type the letters A and /
instead of A and T.

<CR> END-OF-LINE CHARACTER:

This character is typed to end a command line. The value of the <CR> character
is stored in S-register S3. The default value is 13 (the ASCII carriage return character).
When the <CR> character is entered, the modem executes the commands in the
command line.

STARTING A SESSION:
 • Type ATI3<CR> to the modem command line to check the version of the board
being used. This command returns the following result:
Z02215 Ver: V2.0
Z02202 Ver: 50

01-March-2007.
OK

This procedure is not required to start a session, but it ensures that the setup is
correct before the user continues.

• Type ATI4<CR> to the modem command line to check the country configuration
of the firmware. This command returns the following result:
ZiLOG/Softart V.22bis Modem Control for North America
OK

This step displays the current country profile. This step is not required to start a
session.

• Type the following to the modem command line to start dialing into the BBS (1-
408-292-0522).

ATDT9, 14082920522<CR>

The Embedded Modem Evaluation Board can be used to dial any other remote
modem with ATDT<number>. If a 9 must be dialed before making any outgoing calls,
the command is ATDT9, <number>, as depicted in the previous example.

• Wait for 5-10 seconds for the remote modem to answer. When the connection is
established, the modem answers:
CONNECT 2400
 If the remote modem is BUSY, it echoes a BUSY. Try again until a
connection is achieved.
• The modem is now in the ON-LINE mode, connected to the remote modem at a
data rate of 2400bps. At this point, the modem can communicate with the remote
modem and exchange data.

ENDING A SESSION:

The modem may be instructed from the terminal program to disconnect the data
connection, the modem must be brought from DATA mode to COMMAND mode by
typing the Escape Sequence.

• Enter COMMAND mode by typing:

+++

A slight delay is needed for the modem to recognize the Escape Sequence.

Some important AT COMMAND SET:

RESULT CODES:

A result code is a line of text or a number the modem sends to the terminal to
indicate the result of command execution. Some Connect result codes indicate the
telephone line data rate. Table provides a list of the available result codes.
S-REGISTERS:

Modem S-registers contain the values of special purpose ASCII characters, timing
parameters and other modem parameters. The value of an S-register is modified by ATSn
= x, where n is the register number and x is the value to be stored in that particular
register. Each S-register has three values that may be configured for different countries: a
default value, an upper limit, and a lower limit. The values listed in Table are the default
values for North America.
CARRIER DETECTION:

After handshaking, the modem determines if a telephone line connection exists by

detecting the carrier signal from the other modem. If the carrier is not detected for a
specified period of time, the modem presumes the telephone line connection with the
other modem has been broken. The modem uses S-register S9 to determine how long a
carrier must be present before it is detected. The modem uses S-register S10 to determine
how long a carrier may not be detected before the telephone line is disconnected.

TECHNICAL SPECIFICATIONS:
CONFIGURATIONS AND DATA RATES:

The Z02215 can be configured to any of the V.22bis operation modes. Table
provides the selectable options, the supported data rate, and the baud rate, and frequency
to be modulated.

DATA ENCODING:

The data encoding for the Z02215 meets ITU–T recommendations as well as Bell
standards.

TRANSMITTED DATA SPECTRUM:

The transmitted data spectrum, with compromised equalization disabled, is shaped in the
base band of the Finite Impulse Response (FIR) filter. Table reflects the spectrum
characteristics.

ACTIVE HYBRID CIRCUIT AND RELAY DRIVER:

An active hybrid circuit is added to the Analog Front End (AFE) of the Z02215 to
improve the received signal quality level by 20dB and to improve the modem
performance. The on-chip active hybrid reduces system level costs by reducing the
requirement for external components making the designs cost effective and space
efficient. The 2-wire to 4-wire hybrid interfaces to telecom coupling transformers in the
Data Access Arrangement (DAA). The off-hook and shunt relay drivers provide a drive
capability of 30 mA to allow the use of commonly available mechanical telecom relays.

CLOCK OSCILLATOR DESCRIPTION:

The Z02215 on-chip oscillator has a high-gain, parallel-resonant amplifier, for

connection to a crystal (XTAL is Output, EXTAL is Input). The crystal is AT cut, 24.576
MHz, with a series resistance (RS) of less than or equal to 25 Ohms. The crystal is
connected across XTAL and EXTAL using the vendor's recommended capacitor values
from each pin directly to the device Ground pin to reduce ground-noise injection into the
oscillator.

COUNTRY CONFIGURATION:

The Z02215 contains modem controller code that is targeted to operate over a
North America-style telephone network with the DAA configuration illustrated in the
schematics at the end of this product specification. The customer may choose to
configure the modem for use on other telephone networks. This capability is enabled by
the addition of a serial EEPROM to hold various country tables. The EEPROM may be
omitted from the application if the customer chooses to operate with the default North
America-style parameters. If an EEPROM is not desired, the country table can also be
downloaded to the Z02215 from the host and stored in on-board RAM.

he Z02215 provides a means of loading information into the EEPROM for setting
Homologation or country approval tables. One way to set these tables is by choosing the
desired geographic region to be served in a DOS program, supplied by ZILOG, called
Diplomat™. This program interfaces to the modem through theserial port using hidden
AT commands, allowing reprogramming of the EEPROM.

DATA ACCESS ARRANGEMENT:

Isolation transformer (T1) couples the primary (line) and secondary (modem)
sides, while providing high voltage isolation. This wet transformer (allowing DC current)
simplifies the circuit and reduces the cost of the DAA. On the Secondary side, the
transmit (TXA+ and TxA–) and receive (RxA+ and RxA–) are combined in the 4-wire to
2-wire hybrid circuit. On the Primary side, the off-hook relay switches the phone line
between a local handset (phone) or the modem.

The ring detect circuit consists of DC blocking capacitor C304, current limiting
resistor R305, zener diodes CR303 and CR304, optocoupler U303, and its reverse
protection diode D304. Protection elementsRV301, F301, C301, and C302 (and
transformer T1’s isolation) provide higher voltage capability for approval in some foreign
markets. C201 and C202, for example, may require replacement by Metal Oxide
Varistors (MOVs) or Gas Discharge Tubes (GDTs). The shunt relay reduces the DAA
impedance during pulse dialing. This relay is required for certain country approvals. The
CID relay provides a signal path (through C4) to receive Caller ID signals without taking
the line off-hook.

Design Chart for Weather Monitoring System

Start

Initialize Serial
Communication, Timersand
Read Temperature and
Interrupts.
Humidity From
SHT11
Initialize
Set
Display
Baud (Sensor)
LCD
Project
rateand
toTitle
1200
RTC
 Read Date and Time From
HT1380 (RTC)

Store Temperature, Humidity,

Date and Time in Memory

Display Temperature, Humidity,

Time and Date on Graphical LCD
M he k
W h ec
em er
od th
is
C

ot
? rN
o
sy
Bu
 NO

After two rings Modem gets

Connected to the modem in the
remote Host and sends data from
the memory

Modem is disconnected