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AtTiny 2313

AtTiny 2313

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Published by flo_af72
AtTiny 2313
AtTiny 2313

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Categories:Types, Brochures
Published by: flo_af72 on Dec 07, 2009
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10/21/2011

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Features
Utilizes the AVR
 ® 
RISC Architecture
AVR – High-performance and Low-power RISC Architecture –120 Powerful Instructions – Most Single Clock Cycle Execution –32 x 8 General Purpose Working Registers –Fully Static Operation –Up to 20 MIPS Throughput at 20 MHz
Data and Non-volatile Program and Data Memories –2K Bytes of In-System Self Programmable FlashEndurance 10,000 Write/Erase Cycles –128 Bytes In-System Programmable EEPROMEndurance: 100,000 Write/Erase Cycles –128 Bytes Internal SRAM –Programming Lock for Flash Program and EEPROM Data Security
Peripheral Features –One 8-bit Timer/Counter with Separate Prescaler and Compare Mode –One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Modes –Four PWM Channels –On-chip Analog Comparator –Programmable Watchdog Timer with On-chip Oscillator –USI – Universal Serial Interface –Full Duplex USART
Special Microcontroller Features –debugWIRE On-chip Debugging –In-System Programmable via SPI Port –External and Internal Interrupt Sources –Low-power Idle, Power-down, and Standby Modes –Enhanced Power-on Reset Circuit –Programmable Brown-out Detection Circuit –Internal Calibrated Oscillator
I/O and Packages –18 Programmable I/O Lines –20-pin PDIP, 20-pin SOIC, 20-pad QFN/MLF
Operating Voltages –1.8 - 5.5V (ATtiny2313V) –2.7 - 5.5V (ATtiny2313)
Speed Grades –ATtiny2313V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V –ATtiny2313: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V
Typical Power Consumption –Active Mode1 MHz, 1.8V: 230 µA32 kHz, 1.8V: 20 µA (including oscillator) –Power-down Mode< 0.1 µA at 1.8V
8-bit
Microcontrollerwith 2K BytesIn-SystemProgrammableFlash
ATtiny2313/VPreliminary
Rev. 2543I–AVR–04/06
 
2
ATtiny2313/V
2543I–AVR–04/06
Pin Configurations
Figure 1.
Pinout ATtiny2313
Overview
The ATtiny2313 is a low-power CMOS 8-bit microcontroller based on the AVRenhanced RISC architecture. By executing powerful instructions in a single clock cycle,the ATtiny2313 achieves throughputs approaching 1 MIPS per MHz allowing the systemdesigner to optimize power consumption versus processing speed.
(RESET/dW) PA2(RXD) PD0(TXD) PD1(XTAL2) PA1(XTAL1) PA0(CKOUT/XCK/INT0) PD2(INT1) PD3(T0) PD4(OC0B/T1) PD5GND
2019181716151413121112345678910
VCCPB7 (UCSK/SCL/PCINT7)PB6 (MISO/DO/PCINT6)PB5 (MOSI/DI/SDA/PCINT5)PB4 (OC1B/PCINT4)PB3 (OC1A/PCINT3)PB2 (OC0A/PCINT2)PB1 (AIN1/PCINT1)PB0 (AIN0/PCINT0)PD6 (ICP)
PDIP/SOIC
12345
MLF
1514131211
   2   0   1   9   1   8   1   7   1   6   67891   0
(TXD) PD1XTAL2) PA1(XTAL1) PA0(CKOUT/XCK/INT0) PD2(INT1) PD3
   (   T   0   )   P   D   4   (   O   C   0   B   /   T   1   )   P   D   5   G   N   D   (   I   C   P   )   P   D   6   (   A   I   N   0   /   P   C   I   N   T   0   )   P   B   0
PB5 (MOSI/DI/SDA/PCINT5)PB4 (OC1B/PCINT4)PB3 (OC1A/PCINT3)PB2 (OC0A/PCINT2)PB1 (AIN1/PCINT1)
   P   D   0   (   R   X   D   )   P   A   2   (   R   E   S   E   T   /   d   W   )   V   C   C   P   B   7   (   U   C   S   K   /   S   C   K   /   P   C   I   N   T   7   )   P   B   6   (   M   I   S   O   /   D   O   /   P   C   I   N   T   6   )
NOTE: Bottom pad should be soldered to ground.
 
3
ATtiny2313/V
2543I–AVR–04/06
Block Diagram
Figure 2.
Block Diagram
PROGRAMCOUNTERPROGRAMFLASHINSTRUCTIONREGISTERGNDVCCINSTRUCTIONDECODERCONTROLLINESSTACKPOINTERSRAMGENERALPURPOSEREGISTERALUSTATUSREGISTERPROGRAMMINGLOGICSPI8-BIT DATA BUSXTAL1XTAL2RESETINTERNALOSCILLATOROSCILLATORWATCHDOGTIMERTIMING ANDCONTROLMCU CONTROLREGISTERMCU STATUSREGISTERTIMER/ COUNTERSINTERRUPTUNITEEPROMUSIUSART
     A     N     A     L     O     G     C     O     M     P     A     R     A     T     O     R
DATA REGISTERPORTBDATA DIR.REG. PORTBDATA REGISTERPORTADATA DIR.REG. PORTAPORTB DRIVERSPB0 - PB7PORTA DRIVERSPA0 - PA2DATA REGISTERPORTDDATA DIR.REG. PORTDPORTD DRIVERSPD0 - PD6ON-CHIPDEBUGGERINTERNALCALIBRATEDOSCILLATOR

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