Linearity and Speed Optimization in SOILDMOS using Gate Engineering
Radhakrishnan Sithanandam and M. Jagadesh Kumar
The major challenge the RF LDMOS faces today is the linearity and switching delay. In this paper, we propose a new, gate engineered SOI LDMOS device to overcome this problem. The proposed device has three gates arranged in stepped manner, from channel to drift region. Thefirst gate uses p
poly (near the source), whereas the other two gates have n
poly. The first gatewith a thin gate oxide achieves good control over channel charge. The third gate with a thick gateoxide at the drift region achieves reduced gate to drain capacitance. The arrangement of secondand third gate in stepped manner in the drift region spreads the electric field uniformly. Usingtwo dimensional device simulations, the proposed LDMOS is compared with the conventionalLDMOS. We demonstrate that the proposed device exhibits significant enhancements inlinearity, switching delay, breakdown voltage, on-resistance, peak transconductance and gate-drain charge making it highly suitable for RF power amplifiers.
LDMOS, SOI, linearity, breakdown voltage, transconductance, gate charge, switching speed.
The authors are with the Department of Electrical Engineering, Indian Institute of Technology, Delhi 110 016, India (e-mail:email@example.com).
Radhakrishnan Sithanandam and M. Jagadesh Kumar “Linearity and speed optimization inSOI LDMOS using gate engineering,”
Semiconductor Science and Technology,
Vol.25,Article No. 015006, January