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Trends in Low-Power VLSI Design

Trends in Low-Power VLSI Design

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Published by Aaron Merrill
Trends in Low-Power VLSI Design
Trends in Low-Power VLSI Design

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Published by: Aaron Merrill on Dec 12, 2009
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05/10/2013

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5
Trends in Low-Power VLSI Design
Tarek Darwish andMagdy Bayoumi
The Center for Advanced ComputerStudies, University of Louisianaat Lafayette, Lafayette, Louisiana,USA
5.1 Introduction .......................................................................................2635.2 Importance of Low-Power CMOS Design ................................................2635.3 Sources of Power Consumption in CMOS ...............................................2665.3.1 DynamicPower Dissipation • 5.3.2 Short Circuit Power Dissipation •5.3.3 Static Power Dissipation5.4 Power Consumption Considerations .......................................................2705.4.1 SupplyVoltage Level 5.4.2 DeviceThreshold Voltage 5.4.3 PhysicalCapacitance • 5.4.4 Switching Frequency5.5 Energy Versus Power ............................................................................2715.6 Optimization Metrics ...........................................................................2725.7 Techniques for Power Reduction ............................................................2725.7.1 SystemLevel 5.7.2 Architectural Level 5.7.3 LogicGate Level 5.7.4 Circuit Level 5.7.5 Physical LevelReferences ..........................................................................................279
5.1 Introduction
As advances in lithography and fabrication of the N-type metaloxide superconductor (NMOS) technology became possible inthe 1970s, the bipolar digital logic, transistor-transistor logic(TTL) lost the battle in the digital design world for exactly thesame reasons that caused older technologies, such as thevacuum tube technology, to retire. Circuits implemented inthe NMOS technology outperformed the corresponding TTLcircuits in terms of power dissipation. One of the main aspectsof power consumption is that it puts an upper limit on thenumber of gates that can be reliably integrated on a singlepackage for any technology. As technology advanced, chipsgrew, and it was possible to integrate more functions intoone chip. Just as for TTL, newer technology, called CMOS,threatened to replace NMOS in the 1980s because CMOSproved to consume even less power. With further advances intechnology and fabrication, the integration densities and therate at which chips operate have increased drastically, causingpower consumption to be of primary concern. In addition, thenew requirements set by device portability, reliability, and costshave helped in alleviating the power consumption threat inCMOS circuits. Because the power problem is getting more
Copyright © 2005 by Academic Press.All rights of reproduction in any form reserved.
concerning, very large-scale integrated circuit (VLSI) designersneed to develop new efficient techniques to reduce the powerdissipation in current and future technologies, a task that isfull of challenges but yet exciting to explore.
5.2 Importance of Low-Power CMOSDesign
With advances in CMOS technology, the potential packingdensities increase as the feature size of the MOS devicesshrinks, as shown in Figure 5.1. These increases and decreasesvalidate what Gordon Moore once said in the 1960s: thenumber of transistors that can be integrated on a single diewould grow exponentially with time (Moore, 1965). Theexample that amazingly proved his visionary prediction isbest illustrated by tracking the historical evolution of inte-grated circuit (IC) design in the company he founded in1972, Intel, and by using the trends in memory evolution.Such observations are evident in Figure 5.2. Figure 5.2(A)shows the trend in the IC logic complexity evolution for Intelprocessors in the last two decades, whereas Figure 5.2(B) showsthe memory integration density as a function of time.263
 
264
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introduction0.251 Current
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1997 1999 2001 2003 2005 2007
Year
(A) Feature Size for Intel Processors50
nm
LGATE
(B) Current Transistor (C) Future Transistor
FIGURE 5.1 Packing Density and Feature Size (A) The curve shows the past, current, and future trends for the feature size of the IntelProcesses. (B) This image shows a transistor laid out in the 0.09 micrometer or 90 nanometer technology. The gate for that transistor is 50nm.(C) The transistor for future processors is shown here. Courtesy of Intel Corporation.This increase in the number of transistors per package allowedmore functions to be integrated and increased the total logicdensity of a chip. For example, Figure 5.3(A) indicates that thelogic density for the Intel microprocessors doubles every processgeneration. At the same time, the frequency of operation hasdramatically increased due to the device scaling, Figure 5.3(B)shows the introduction of performance boosting techniques,such as pipelining, super-pipelining, and parallel architectures.This increase in operating frequency was driven by the need forfast digital systems realizing powerful personal workstations,sophisticated computer graphics, and multimedia capabilities,such as real-time speech recognition and real-time video (Chan-drakasan
et al.,
1992). When CMOS technology was introduced,it was believed that the power consumption problem was solved.The major concerns of the VLSI designer were mainly speed,cost, and reliability; power consideration was mostly of second-ary importance (Pedram, 1995). But as major concerns werebeing met, the power dissipated in a chip has increased from onegeneration to another. Figure 5.4 shows the power dissipation ofthe Intel family of microprocessors.Figure 5.5 shows some projections for future processors ifpower continues to dissipate at the same rate. The figure alsoshows the power density behavior during the last two decades.With the current processors, we have reached the power den-sity of a hot plate. Without limiting power dissipation, we willsomeday have nuclear reactor-equivalent power dissipated inchips we use at home or in our mobile devices!Such observations are in contradiction with the scalingtheory. VLSI technology scaling has evolved at an amazinglyfast pace during the last 30 years; the minimum device size keepsshrinking by a factor k = 0.7 per technology generation. Thebasic scaling theory, known as constant field scaling mandatesthe synergistic scaling of geometric features and silicon dopinglevels to maintain a constant field across the gate oxide of theMOS transistor (Benini
et a l.,
2001; Panasonic, 2000). Accordingto the constant field scaling theory, power dissipation scales as k2and power density (i.e., power dissipated per unit area) remainsconstant while speed increases as k. Such contradiction betweenthe theory and conclusion from Figure 5.4 and Figure 5.5 hastwo causes. First, die size has been steadily increasing withtechnology (Figure 5.6), causing an increase in total averagepower, as shown in Figure 5.4. Second, supply voltage has scaledmuch more slowly than device size because supply voltage levelshave been standardized and because faster transistor operationcan be obtained for higher supply voltage levels.Hence, this large amount of power dissipation is one ofthe main motivations for VLSI designers to develop newtechniques to reduce the power consumed inside chips; power
 
5 Trends in Low-Power VLSI Design
265
Transistors100,000,00010,000,0001,000,000100,00010,0001970 1975
1980 1985 1990
(A) IC Logic Complexity1995100020001.0E+081.0E+07
<
1.0E+06re
~ 1.0E+05
.a
1.0E+04
1.0E+03 1
K1970
DRAMs: memory size
256M
~L K
/
Market introduction*Doubling ime: 18 months
\
256K• 64K
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• 16K
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• 64M
16Mk 1M 4M ~'
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age s~oldbling time: 21 months*First year sales exceed 10*units
i
1975 1980 1985 1990 1995 2000(B) Memory ntegrationDensity
FIGURE 5.2 This Figure Shows the Number of Transistors Per Chip is Increasing. (A) Shows the number of transistors per Intel processor.The horizontal axis shows the time of introducing a chip, and the vertical axis shows the corresponding number of transistors included.Courtesy of Intel Corporation. (B) Shows the number of transistors per DRAM memory chip. Similarly, he horizontal axis shows the time ofintroducing a chip, and the vertical axis shows the corresponding number of transistors included.is being given comparable weight to area and speed consider-ations (Najm, 1994). Several important factors have also con-tributed to this increased concern about power. One of theseprimary driving factors has been the remarkable success andgrowth of the personal computing device (e.g., Pass portabledesktops, audio- and video-based multimedia products, etc.)and wireless communications systems (e.g., personal digitalassistants, personal communicators, etc.) that demand high-speed computation and complex functionality with low-powerconsumption (Pedram, 1995). Unfortunately, this rapid devel-opment in VLSI has not been reflected in developments inbattery technology, and without low-power design techniques,current and future portable devices will suffer from either veryshort battery life or very heavy battery pack (Pedram, 1995;Najm, 1994; Athas
et al.,
1994; Landman and Rabaey, 1995;Tsul
et al.,
1995; Chang and Pedram, 1997; Bajwa
et al.,
1997).It is clear that in the absence of low-power design techniques,portable and handheld products would suffer from a veryshort battery life, and packing and cooling them would bevery difficult (Tsui
et al.,
1995; Ko
et al.,
1995). These factorslead to an unavoidable increase in the cost of the product, asshown in Figure 5.7. In addition, reliability is strongly affected

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