Unit 2: 8086 Microprocessor

Contents:
Instruction execution timing,
Assembler instruction format,
Data transfer instructions,
Arithmetic instructions, branch instructions, looping instructions,
NOP and HLT instructions, flag manipulation instructions, logical
instructions, shift and rotate instructions,
directives and operators, programming examples.

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 8086 Architecture
• The 8086 has

• 20 address lines
• 16 data lines
• 4-10 control lines.

With this the 8086 is able

• To address 1,048,,576 (220 ) memory locations/ports.

• To manipulate and/or operate on 16-bits(2-bytes) of data at a
time.
• To generate necessary control signals
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• The internal architecture of 8086 can be mainly divided into
two units:
• Bus interface unit (biu)
• Execution unit (eu)
• The biu contains :
• Code segment register (cs)
• data segment register (ds)
• extra segment register (es)
• Stack segment registeer (ss) and
• instruction pointer (ip)

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• THE EU CONTAINS THE FOLLOWING 8-BIT REGISTERS:

• AH & AL (AX-16 BIT)

• BH & BL (BX-16 BIT)
• CH & CL (CX-16 BIT)
• DH 7 DL (DX-16 BIT)

• IT ALSO INCLUDES THE FOLLOWING 16-BIT REGISTERS:

• STACK POINTER (SP)
• BASE POINTER (BP)
• SOURCE INDEX (SI)
• DESTINATION INDEX (DI)

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 The Bus Interface Unit (BIU) consists of the following:
• Instruction Queue: this allows the next instructions or data to be
fetched from memory while the processor is executing the current
instruction.
• The memory interface is usually much slower than the processor
execution time, so this decouples the memory cycle time from the
execution time.
• Segment Registers: The Code Segment (CS), Data Segment (DS),
Stack Segment (SS) and Extra Segment (ES) registers are 16-bit
registers, used with the 16-bit Base registers to generate the 20-bit
address required to allow the 8086/8088 to address 1Mb of
memory.
• They are changed under program control to point to different
segments as a program executes.
• The Segmented architecture was used in the 8086 to keep
compatibility with earlier processors such as the 8085.
• It is one of the most significant elements of the Intel Architecture

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15/07/08 Institute of Technology and Management, Gurgaon
 • The Instruction Pointer (IP) and Address Summation: The IP
contains the Offset Address of the next Instruction, which is the
distance in bytes from the base address given by the current Code
Segment (CS) register. The figure shows how this is done.

• The contents of the CS are shifted left by four. Bit 15 moves to the
Bit 19 position. The lowest four bits are filled with zeros. The
resulting value is added to the Instruction Pointer contents to make
up a 20-bit physical address. The CS makes up a segment base
address and the IP is looked as an offset into this segment.

• This segmented model also applies to all the other general registers
and segment registers in the8086 device. For example, the SS and
SP are combined in the same way to address the stack area in
physical memory.

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 This is how memory is accessed using these signals

• This scheme applies even when16-bit memories are used. It allows the 8086
to access byte data. Similar schemes allow 32-bit processors like the 80386
to access byte data.

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 • ALE (Address Latch Enable): On both the 8086 and
8088 processors the address and data buses are
multiplexed. This means that the same pins are used to
carry both address and data information – at different
times during the read or write cycle. At the start of the
cycle the address/data bus carries the address signals,
while at the end of the cycle the pins are used for the data
bus.

• The ALE signal is used to allow external logic to

LATCH the addresses while the AD lines carry address
data and hold those addresses so that they can be applied
to the other devices in the system. The address latch used
are 74HC373 or equivalent parts. Unlike a flip flop, the
74HC373 is a transparent latch.

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15/07/08 Institute of Technology and Management, Gurgaon
 BASIC 8086 MINIMUM MODE SYSTEM

MN/MX
CLK M/IO
8284A
READY
CLOCK INTA
RESET
GENE-
RD
RATOR
WR
8282
DT/R
LATCH
DEN
ALE ADDR
WAIT STATE
GENERATOR AD0-
AD15
A16-A19

8286
TRAN-
ADDR/DATA CEIVER
DATA

RAM 2142 PERI-

2716
PHERAL
PROM

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 Basic signal flow on 8086 buses

• Basically there are two operations to see:

• 1.Read operation
• 2. Write operation
.

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 T1 T2 T3 TW T4

CLK

M/IO

ALE
MEMORY ACCESS TIME
ADDR/ RESERVED VALID
A15-A0
DATA FOR DATA D15-D0

ADDR/ A19-A16
STATUS
RD/INTA
READY
DT/R
DEN
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 WRITE CYCLE
 Here we will see the activities carried out on
8086 bus at various time instants when it
writes to a port or a memory location.
 Assumption that the 8086 is operated in is
minimum mode.

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 T1 T2 T3 TW T4

CLK

M/IO

ALE

ADDR/
A15-A0 DATA OUT (D15-D0)
DATA
ADDR/ A19-A16
STATUS
WR
READY
DT/R
DEN
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 Wait States

• Wait States are used to help interface to slow memory or I/O devices.
• The READY input signal on the 8086 is used to insert wait states into
the processor bus cycle, so that the processor stretches out its read or
write cycle, to accommodate the slow device.
Generating Wait States
• The normal memory or I/O cycle on an 8086 is 4 clocks long – T1 to
T4. Wait states , called Tw can be inserted in the bus cycle as
followsThe 8086 READY line is sampled at the rising edge of T3. If
READY is low, a WAUT state is inserted.
• During the WAIT state the READY is sampled again at the next rising
edge of the clock, and another
• WAIT is inserted if READY is still low. A number of further WAIT
states can be inserted in this way.

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 • The memory or I/O device can initiate WAIT state
generation by bringing a RDY signal low.
• To synchronise the 8086 READY signal and to ensure that
the 8086 timing requirements are met the memory device’s
RDY signal is normally connected to the 8284’s RDY
input.
• The memory device needs to bring RDY low prior to the
rising edge of the 8086’s T2 clock.
• The 8284 drives the 8086 READY signal low at the falling
edge of T2. When the 8086 samples READY at the rising
of T3 it finds that it is low, and it inserts a WAIT state for
the next clock state.
• The memory device has to bring RDY high early in T3 so
that the 8284 can bring READY high before the rising edge
of T3 if another WAIT state is to be avoided.

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 8086 PHYSICAL MEMORY
• The total memory (1mb) of 8086 is arranged in two banks. An
odd bank and an even bank. Both the banks have equal no. Of
locations.

• The odd bank contains odd numbered mem. Locations.It is known

as upper bank.

• The even bank contains only even numbered mem. Locations.It is

known as lower bank.

• This arrange ment is done in order to speed up the operation.

• The arrangement and the signal followed, explains the same.

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 THE 8086 MEMORY BANK
UPPER BANK LOWER BANK

ODD EVEN

CS CS

BHE A1---A19 A0
D15-D8 D7-D0

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 ADDRESSING WITH 8086
 PROBLEM: TWO 16K ROM AND TWO 32K RAM ARE
REQUIRED TO BE INTERFACED WITH 8086 CPU.THE
RAM ADDRESS MUST START AT 00000H.THE ROM
ADDRESS RANGE MUST INCLUDE FFFF0H IN ITS
RANGE.

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 ADDRESS MAP
• The ram address starts at 00000h.

• Total ram is 2*32k.So ram address range is from 00000h to

0ffffh.(Ffff-0000)h=216 =64k.Since the rom address must
include ffff0h. We take last address of rom as fffffh.

• As total space for rom is 2*16k,the first address for rom is

f8000h. (Fffff-f8000)h=215=32k.

• Address lines a1-a14 are connected to rom.Address lines

a1-a15 are connected to ram.And remaining lines are used
for chip selection.(Note: a0 is reserved for banks.)

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• To generate the chip select signal the following logic is
used:
• The chipselect signal is active low.So a particular chip
can be selected only when this signal is low.
• Secondly at a time only one chip should be selected.
• Further ,the odd bank will be enabled only if bhe signal
is activated.And the even bank will be enabled only if ao
signal is low.

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 Memory Segmentation
• Since the 8086 has only 16-bit registers, its Mega (220) byte
of address space is split into segments - logical units of
memory that may be up to 64K (216) bytes long. Each
segment is made up of contiguous memory locations and is an
independent, seperately-addressable unit. Every segment is
assigned (by software) a base address, which is its starting
location in the memory space. Apart from having to begin on
16-byte memory boundaries, there are no restrictions on
segment locations.
Physical Address Generation
• Every memory location has two kinds of address - physical
and logical. A physical address is the 20-bit value that
uniquely identifies each byte location in the Megabyte
memory space. These may range from 0 to FFFFF Hex. All
exchanges between the CPU and memory components use this
physical address.
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 • Programs deal with logical, rather than physical, addresses. A
logical address consists of a segment base value and an offset
value.
• For any given memory location, the segment base value
locates the first byte of the containing segment and the offset
value is the distance, in bytes, of the target location from the
beginning of the segment.
• Segment base and offset values are unsigned 16-bit quantities;
the lowest-addressed byte in a segment has an offset of 0.
Whenever memory is accessed, a physical address is generated
from a logical address.
• This is done by shifting the segment base value four bit
positions to the left (hence 16 (24) -byte boundaries) and
adding the offset, as illustrated.

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 8086 Addressing Modes

• The 80x86 processors let you access memory in many

different ways. The 80x86 memory addressing modes provide
flexible access to memory, allowing you to easily access
variables, arrays, records, pointers, and other complex data
types. Mastery of the 80x86 addressing modes is the first step
towards mastering 80x86 assembly language. When Intel
designed the original 8086 processor, they provided it with a
flexible, though limited, set of memory addressing modes

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 1) 8086 Register Addressing Modes

• Most 8086 instructions can operate on the 8086's

general purpose register set. By specifying the name of
the register as an operand to the instruction, you may
access the contents of that register.
• Consider the 8086 mov (move) instruction:
mov destination, source
• This instruction copies the data from the source operand
to the destination operand.
• The eight and 16 bit registers are certainly valid
operands for this instruction. The only restriction is that
both operands must be the same size.

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 2) 8086 Memory Addressing Modes

• The 8086 provides 17 different ways to access memory. This

may seem like quite a bit at first, but fortunately most of the
address modes are simple variants of one another so they're
very easy to learn. And learn them you should! The key to
good assembly language programming is the proper use of
memory addressing modes.
• The addressing modes provided by the 8086 family include
displacement-only, base, displacement plus base, base plus
indexed, and displacement plus base plus indexed.

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 i) Displacement Only Addressing Mode

The displacement-only addressing mode consists of a 16

bit constant that specifies the address of the target
location. The instruction mov al,ds:[8088h] loads the al
register with a copy of the byte at memory location
8088h. Likewise, the instruction mov ds:[1234h],dl stores
the value in the dl register to memory location 1234h.
The displacement-only addressing mode is perfect for
accessing simple variables
•

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 ii) Register Indirect Addressing Modes

• The 80x86 CPUs let you access memory indirectly through a

register using the register indirect addressing modes. There are
four forms of this addressing mode on the 8086, best
demonstrated by the following instructions:
mov al, [bx]
mov al, [bp]
mov al, [si]
mov al, [di]

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 • As with the x86 [bx] addressing mode, these four addressing
modes reference the byte at the offset found in the bx, bp, si,
or di register, respectively. The [bx], [si], and [di] modes use
the ds segment by default. The [bp] addressing mode uses the
stack segment (ss) by default.
iii) Indexed Addressing Modes
• The indexed addressing modes use the following syntax:
mov al, disp[bx]
mov al, disp[bp]
mov al, disp[si]
mov al, disp[di]
If bx contains 1000h, then the instruction mov cl,20h[bx] will
load cl from memory location ds:1020h. Likewise, if bp
contains 2020h, mov dh,1000h[bp] will load dh from location
ss:3020.

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 The offsets generated by these addressing modes are the sum of
the constant and the specified register. The addressing modes
involving bx, si, and di all use the data segment, the disp[bp]
addressing mode uses the stack segment by default.

iv) Based Indexed Addressing Modes

• The based indexed addressing modes are simply combinations
of the register indirect addressing modes. These addressing
modes form the offset by adding together a base register (bx or
bp) and an index register (si or di). The allowable forms for
these addressing modes are
mov al, [bx][si]
mov al, [bx][di]
mov al, [bp][si]
mov al, [bp][di]
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 v) Based Indexed Plus Displacement Addressing Mode

• These addressing modes are a slight modification of the

base/indexed addressing modes with the addition of an eight
bit or sixteen bit constant. The following are some examples
of these addressing modes:
mov al, disp[bx][si]
mov al, disp[bx+di]
mov al, [bp+si+disp]
mov al, [bp][di][disp]

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