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Simulation, Analysis and Comparison of SET and CMOS Hybrid Circuits

Simulation, Analysis and Comparison of SET and CMOS Hybrid Circuits

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Published by: Colin Valentine on Dec 15, 2009
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Simulation, Analysis and Comparison of SET AndCMOS Hybrid Circuits Using SPICE Model
G.V.Hari Prasad Dr.P.Rajesh kumar V.srinivasa Rao K.Leela BhavaniEmail:leelaklb@gamil.com,gvh.prasad2k@gmail.com
 
 Department Of Electronics & Communication Engineering Shri Vishnu Engineering College For Women,JNTU Kakinada University
 
Abstract
A tunneling transistor is considered to be an element of a futurelow power, high-density integrated circuit because of a possibleultra-low power operation with a few electrons. In this context,the performance of SET is compared qualitatively andquantitatively with CMOS logic gates. Therefore, although acomplete replacement of CMOS by single-electronics isunlikely in the near future, it is also true that combining SETand CMOS one can bring out new functionalities, which are un-mirrored in pure CMOS technology. As the hybridization of CMOS and SET is gaining popularity, silicon SETs areappearing to be more promising than metallic SETs for their  possible integration with CMOS Simulation of SET and CMOScircuits are required for efficient circuit design and analysis.The macro-modeling technique of SET has been applied to theSPICE simulation of single-electron/CMOS hybrid circuits.
Keywords
Coulomb Blockade, Single ElectronTransistor,CMOS, Hybrid circuits, SPICE
Introduction
Recently, there has been great progress in the fabrication of various nano-devices utilizing silicon ULSI processingtechniques. Reliable room temperature operations have beendemonstrated in a silicon single-electron quantum-dot transistor,a silicon self assembled quantum-dot transistor, and varioustypes of single-electron memory cells. SETs have been widelystudied and demonstrated due to the maturity and variety of their process technologies. These devices based on the single-electron charging effect, i.e., the Coulomb blockade in Sinanostructures, are promising because their operation principle becomes more robust as the device size is scaled down unlikeMOSFET, which will be further explained in the followingsection. Moreover, their power consumption is quite low.However, SETs are not expected to replace the conventionalCMOS logic devices because of their inherent limitations suchas a low voltage gain and current drivability. In contrast, newfunctionalities of SETs, such as quantum cellular automata(QCA), binary decision diagram (BDD) devices, and the multivalued logic, have been explored extensively.Single-electron tunneling transistor is a device that exploitsthe quatum effect of tunneling to control and measure themoment of single electrons.Unlike field-effect transistors,single-electron devices are based on an intrinsically quantum phenomenon: the tunnel effect. This is observed when tometallic electrodes are separated by an insulating barrier about1nm thick. Electrons at the Fermi energy can “tunnel” throughthe insulator, even though in classical terms their energy would be low to overcome the potential barrier.The SET transistor can be viewed as an electron box thathas two separate junctions for the entrance and exit of singleelectrons.Fig 1: A Single-electron transistor diagramFor an electron to hop onto the island, its energy must equalthe Coulomb energy
e
2/2
. When both the gate and biasvoltages are zero, electrons do not have enough energy to enter the island and current does not flow. As the bias voltage between the source and drain is increased, an electron can passthrough the island when the energy in the system reaches theCoulomb energy. This effect is known as the Coulomb blockade, and the critical voltage needed to transfer an electrononto the island, equal to
e
/
, is called the Coulomb gap voltage.If the bias voltage is kept below the Coulomb gap voltage theincrease of gate voltage gradually increases the energy of theinitial system while the energy of the system with one excesselectron on the island gradually decreases. At the gate voltagecorresponding to the point of maximum slope on the Coulombstaircase, both of these configurations equally qualify as thelowest energy states of the system. This lifts the Coulomb blockade, allowing electrons to tunnel into and out of the island.There are three fundamentally different approaches to thesimulation of single electron circuits: SPICE macro-modeling,Monte Carlo based and Master Equation based .In this paper,the Simulation of SET and CMOS based logic circuits are done by Micro-Cap Simulator. The commonly used simulators areMOSES, SIMON, and KOSEC. These simulators are based ona Monte Carlo method. Micro-Cap is a SPICE compatiblemethod. The SPICE macro-modeling of SET has beensuccessfully applied to the simulation of single-electron/hybridcircuits. Several hybrid circuits such as an SET-NMOS pair anda single electron NOR-gate with CMOS bu
ff 
ers have been
 
simulated and e
ffi
cient interface characteristics aredemonstrated.
REVIEW OF SPICE MACRO-MODELINGOF SETS
SPICE simulation of SET circuits is possible by the macromodeling of SETs. The macro modeling scheme is compatiblewith the standard method of SPICE simulation, consisting of thedevice modeling using an equivalent circuit, parameteextraction and subsequent circuit simulation. Figure 2 shows theschematic diagram of an SET and its equivalent circuit. Themacro-model representation of the equivalent circuit issummarized in Fig.2In Fig. 2, R1 , R2 , and R3 is expressed with a cosinefunction to describe the Coulomb oscillationAnd D2, D3, Vp, and −Vp are expressed to describe theCoulomb staircase. The parameter values, CF 1 = 60,CV p =0.015, CI2 = 0.2 × 10−9 , CR1 = 300 × 106 , and CR2 = 100 ×106 , give the best fit of the current-voltage characteristics whenC = 1.6 aF, Cg = 4.8 aF, Rt =100 M Ω, and T = 30 K.Fig 2 a. Macro –modeling of an SET (equivalent circuit of anSET)
 
SIMULATION OF SET & CMOS BASEDLOGIC GATES
 We can construct single-electron logic circuits in which SETscan operate analogously to MOSFETs of CMOS logic circuits.The Simulation of SET and CMOS based logic circuits are done by Micro-Cap and SPICE software respectively.Since most of the readers are very familiar with CMOS logiccircuits,Schematic of SET logic circuits only are presentedhere.. 
Inverter
Complementary single-electron inverter,afundamental circuit element for single-electron CMOS-typelogic can be constructed by using twp similar SETs. Anequivalent circuit is shown in Fig.3 Each SET has two gates.One of them acts as an input gate, and other acts as a controlgate by which we can use the same SET as a p-switch or an n-switch. Fig.3. SET based inverter schematic Let us first assume the followings for the inverting buffer circuit, as depicted in Fig.2. logic ‘0’=Vd=0mv, logic‘1’=Vd=Vs~qe/C1.The inverting buffer is composed of 2 SETtransistors, where the upper transistor T1 consists of the circuitelements J1,J2,Cg1,Cb1 and the lower transistor T2 consists of the circuit elements J3,J4,Cg2,Cb2.When the buffer’s output values changes, a chargetransport of 1qe occurs through one of these two transistors.theinitial tunnel event occurs in either junction J1 (followed by atunnel event in junction J2), or in junction J4 (followed by atunnel event in junction J3).In each of these two cases, the delayassociated with the initial tunnel event is approximately oneorder of magnitude larger than the delay of the second tunnelevent. The total capacitive load attached to a transistor island(nodes n1 and n3) is assumed to be approximately ½[C1].As aresult, the critical voltage Vc of each tunnel junction isapproximately Vs, Focusing on T1,and assuming that the inputVin is logic ‘0’ and that the charges on nodes n1 and n2 are both 0, the initial tunnel event occurs through J1. Afterwards,the charge on node n1 is qe while the charge on node n2remains 0.Consequently, the voltage across junction J2 resultingfrom the initial tunnel event is approximately Vs. In contrast theinitial tunnel event in J1 is triggered when the input Vinswitches between logic ‘0’ and ‘1’.The Fig.4. Shows the Screenshot of SET inverter using Micro-cap.
 
 Fig.4. Screen shot-SET inverter in Micro-capFig .5.Inverter input & output waveformsFig.5.shows the CMOS based inverter input & outputwaveforms. From these waveforms it’s very clear that the SET based inverter switches very fast without much delay andvoltage swing.Fig.6 & Fig.7 shows the waveforms of NANDand NOR.Fig. 6. SET- NAND input & output waveformsFig. 7. SET- NOR input & output waveforms
 
SIMULATION OF SET/CMOS HYBRIDCIRCUITS
Figure 8 shows two typical examples of hybrid circuits.Figure 8(a) shows an inverter consisting of an SET with an NMOS load. The bias voltage (Vdd) is 0.015 V and the gate bias of the NMOS load (Vgg) is 0.5 V so that the NMOS loadoperates in the sub threshold region. The output of the inverter is connected to the 3-stage CMOS bu
ff 
ers. Figure 8(b) shows ahybrid circuit consisting of a single electron NOR-gateconnected with 4-stage CMOS bu
ff 
ers. The parameters of MOStransistors are notified in the figure where Wn , Wp , L, tox , VT N , and VT P denote the NMOS channel width, the PMOSchannel width, the channel length, the gate oxide thickness, the NMOS threshold voltage, and the PMOS threshold voltage,respectively. The channel widths of the first CMOS inverter arenarrower than those of the others to reduce the load capacitanceseen by the SEC. Multi-stage CMOS bu
ff 
ers are used for theamplification of the output signal (Vout ) up to the full swing(±1 V).

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