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Vhdl Code for Updown Cnt

Vhdl Code for Updown Cnt

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Published by: meaow88 on Dec 16, 2009
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04/05/2013

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VHDL CODE FOR 4-BIT UPDOWN COUNTER :
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity up_dn_beh4 isPort ( clk,rst : in STD_LOGIC;u_d : in STD_LOGIC;q : out STD_LOGIC_VECTOR (3 downto 0));end up_dn_beh4;architecture Behavioral of up_dn_beh4 issignal cnt: std_logic_vector (3 downto 0);signal en : std_logic; beginq <= cnt;P1:process(clk) beginif(clk ' event and clk = '1') thenif (rst = '1') then cnt <= "0000";elsif (u_d = '1' and en = '1') then cnt <= cnt + 1;elsif (en = '0') then cnt <= cnt - 1;end if;end if;end process P1;P2: process(cnt)
 
 beginif (cnt = "0000") then en <= '1';elsif (cnt = "1111") then en <= '0';end if;end process P2;end Behavioral;
FIG3.2 WAVEFORM FOR UP DOWN COUNTER 

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It is very clear except the wave form. To the point and simple. Thank you
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