speak ofmemory capacities in terms ofbits,since a separate flip-flop or other sim-ilar circuit is used to store each bit.On the other hand,system designers usually statememory capacities in terms of
(8 bits);each byte represents a single alphanu-meric character.Very large scientific computing systems often have memory capac-ity stated in terms of
(32 to 128 bits).Each byte or word is stored in a partic-ular location that is identified by a unique numeric
.Memory storagecapacity is usually stated in units ofkilobytes (K bytes) or megabytes (M bytes).Because memory addressing is based on binary codes,capacities that are integralpowers of2 are most common.Thus the convention is that,for example,1K byte
1,024 bytes and 64K bytes
65,536 bytes.In most memory systems,only a singlebyte or word at a single address is stored or retrieved during each cycle ofmemory operation.
memories are also available that have the ability to read/writetwo words in one cycle.
The preferred organization for most large memories is shown in Figure 8.1.Thisorganization is a
architecture.The name is derived from the fact thatmemory locations (
) can be accessed in random order at a fixed rate,inde-pendent ofphysical location,for reading or writing.The storage array,or
,ismade up ofsimple cell circuits arranged to share connections in horizontal rowsand vertical columns.The horizontal lines,which are driven only from outside thestorage array,are called
,while the vertical lines,along which data flow intoand out ofcells,are called
.A cell is accessed for reading or writing by selecting its row and column.Eachcell can store 0 or 1.Memories may simultaneously select 4,8,16,32,or 64 columns
ANALYSIS AND DESIGN OF DIGITAL INTEGRATED CIRCUITS
R o w d e c o d e r R o w a d d r e s s
Column decoder/MUXCell arrayColumn address111
Organization of memory systems.