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serial peripheral interface bus - wikipedia, the free encyclopedia

serial peripheral interface bus - wikipedia, the free encyclopedia

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Published by: Manit on Jan 06, 2010
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SPI bus: single master and single slave
Serial Peripheral Interface Bus
From Wikipedia, the free encyclopedia
Serial Peripheral Interface Bus
(often pronounced "es-pē-ī" [IPA:
s pi: 'a
] or"spy" [IPA: spa
]) bus is asynchronousserial datalink standard named byMotorola that operates infull duplex mode. Devices communicate inmaster/slave mode where the master deviceinitiates thedata frame. Multiple slave devices areallowed with individualslave select (chip select)lines. Sometimes SPI is called a "four wire" serial bus, contrasting withthree,two, andone wire serial buses.
1Interface2Operation2.1Data Transmission2.1.1Clock polarity and phase2.1.2Mode Numbers2.2Independent slave SPI configuration2.3Daisy chain SPI configuration2.4Valid SPI communications2.5Interrupts2.6Example of bit-banging the SPI Master protocol3Pros and cons of SPI3.1Advantages3.2Disadvantages4Applications5Standards6Development Tools6.1Hardware Interfaces6.2Protocol Analyzers7Related Terms7.1Queued Serial Peripheral Interface (QSPI)7.2Microwire7.33-Wire Serial Buses8References9See also10External links
11/7/2009Serial Peripheral Interface Bus - Wikipewikipedia.org//Serial_Peripheral_In1/11
The SPI bus specifies four logic signals.SCLK — Serial Clock (output from master)MOSI/SIMO — Master Output, Slave Input (output from master)MISO/SOMI — Master Input, Slave Output (output from slave)SS Slave Select (active low; output from master)Alternative naming conventions are also widely used:SCK, CLK — Serial Clock (output from master)SDI, DI, SI — Serial Data In, Data In, Serial InSDO, DO, SO — Serial Data Out, Data Out, Serial OutnCS, CS, nSS, STE —Chip Select, Slave Transmit Enable (active low; output from master)The SDI/SDO (DI/DO, SI/SO) convention requires that SDO on the master be connected to SDI on the slave,and vice-versa. Chip select polarity is rarely active high, although some notations (such as SS or CS instead of nSSor nCS) suggest otherwise.
SPI port pin names for particular IC products may differ from those depicted in these illustrations.
The SPI bus can operate with a single master device and with one or more slave devices.If a single slave device is used, the SS pin
be fixed tologic low if the slave permits it. Some slaves require thefalling edge (high->low transition) of the slave select to initiate an action such as the MAX1242 byMaxim, anADC, that starts conversion on said transition. With multiple slave devices, an independent SS signal is requiredfrom the master for each slave device.Most slave devices havetri-state outputs so their MISO signal becomeshigh impedance ("disconnected") when thedevice is not selected. Devices without tristate outputs can't share SPI bus segments with other devices; only onesuch slave could talk to the master, and only its chipselect could be activated.
Data Transmission
To begin a communication, the master firstconfigures the clock, using a frequency lessthan or equal to the maximum frequency theslave device supports. Such frequencies arecommonly in the range of 1-70 MHz.The master then pulls the slave select lowfor the desired chip. If a waiting period isrequired (such as for analog-to-digital
11/7/2009Serial Peripheral Interface Bus - Wikipewikipedia.org//Serial_Peripheral_In2/11
A typical hardware setup using twoshift registers to form an inter-chipcircular bufferA timing diagram showing clock polarity and phase
conversion) then the master must wait for atleast that period of time before starting toissue clock cycles.During each SPI clock cycle, afull duplex data transmission occurs:the master sends a bit on the MOSI line; the slave reads it from that same linethe slave sends a bit on the MISO line; the master reads it from that same lineNot all transmissions require all four of these operations to be
but they do happen.Transmissions normally involve two shift registers of some given word size, such as eight bits, one in the master andone in the slave; they are connected in a ring. Data is usually shifted out with the most significant bit first, whileshifting a new least significant bit into the same register. After that register has been shifted out, the master and slavehave exchanged register values. Then each device takes that value and does something with it, such as writing it tomemory. If there is more data to exchange, the shift registers are loaded with new data and the process repeats.Transmissions may involve any number of clock cycles. When there is no more data to be transmitted, the masterstops toggling its clock. Normally, it then deselects the slave.Transmissions often consist of 8-bit words, and a master can initiate multiple such transmissions if it wishes/needs.However, other word sizes are also common, such as 16-bit words for touchscreen controllers or audio codecs,like the TSC2101 fromTexas Instruments; or 12-bit words for many digital-to-analog or analog-to-digitalconverters.Every slave on the bus that hasn't been activated using its slave select line must disregard the input clock and MOSIsignals, and must not drive MISO. The master must select only one slave at a time.
Clock polarity and phase
In addition to setting the clock frequency,the master must also configure the clock polarity and phase with respect to the data.Freescale's SPI Block Guide
namesthese two options as CPOL and CPHArespectively, and most vendors haveadopted that convention.Thetiming diagram is shown to the right.The timing is further described below andapplies to both the master and the slavedevice.At CPOL=0 the base value of theclock is zeroFor CPHA=0, data are readon the clock'srising edge (low->high transition) and data are changed on afalling edge (high->lowclock transition).For CPHA=1, data are read on the clock's falling edge and data are changed on a rising edge.
11/7/2009Serial Peripheral Interface Bus - Wikipewikipedia.org//Serial_Peripheral_In3/11

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