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ASSIGNMENT No: 1
Title of Assignment: Study of 8086 pin diagram. Write an Assembly Language Program
(ALP) in 8086 to add an array of N nos. stored in the memory
Relevant Theory:
Pin functions:
• AD15-AD0
o Multiplexed address(ALE=1)/data bus(ALE=0).
• A19/S6-A16/S3 (multiplexed)
o High order 4 bits of the 20-bit address OR status bits S6-S3.
• M/IO
o Indicates if address is a Memory or IO address.
• RD
o When 0, data bus is driven by memory or an I/O device.
• WR
o Microprocessor is driving data bus to memory or an I/O device.
When 0, data bus contains valid data.
• ALE (Address latch enable)
o When 1, address data bus contains a memory or I/O address.
• DT/R (Data Transmit/Receive)
o Data bus is transmitting/receiving data.
• DEN (Data bus Enable)
o Activates external data bus buffers.
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• INTR
o When 1 and IF=1, microprocessor prepares to service interrupt. INTA
becomes active after current instruction completes.
• INTA
o Interrupt Acknowledge generated by the microprocessor in
response to INTR. Causes the interrupt vector to be put onto the data
bus.
• NMI
o Non-maskable interrupt. Similar to INTR except IF flag bit is not
consulted and interrupt is vector 2.
• CLK
o Clock input must have a duty cycle of 33% (high for 1/3 and low for
2/3s)
• VCC/GND
o Power supply (5V) and GND (0V).
• MN/ MX
o Select minimum (5V) or maximum mode (0V) of operation.
• BHE
o Bus High Enable. Enables the most significant data bus bits (D 15 -D 8
) during a read or write operation.
• READY
o Used to insert wait states (controlled by memory and IO for
reads/writes) into the microprocessor.
• RESET
o Microprocessor resets if this pin is held high for 4 clock periods.
o Instruction execution begins at FFFF0H and IF flag is cleared.
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• TEST
o An input that is tested by the WAIT instruction.
o Commonly connected to the 8087 coprocessor.
• HOLD
o Requests a direct memory access (DMA). When 1, microprocessor
stops and places address, data and control bus in high-impedance
state.
• HLDA (Hold Acknowledge)
o Indicates that the microprocessor has entered the hold state.
• RO/GT1 and RO/GT0
o Request/grant pins request/grant direct memory accesses (DMA)
during maximum mode operation.
• LOCK
o Lock output is used to lock peripherals off the system. Activated by
using the LOCK: prefix on any instruction.
• QS1 and QS0
The queue status bits show status of internal instruction queue. Provided for access by the numeric
coprocessor (8087).
(B) Assembly Language Program (ALP) in 8086 to add an array of N nos. stored in
the memory:
The Microsoft Macro Assembler (abbreviated MASM) is an assembler for the x86
family of microprocessors. It was originally produced by Microsoft for development
work on their MS-DOS operating system, and was for some time the most popular
assembler available for that operating system. It supported a wide variety of macro
facilities and structured programming idioms, including high-level constructions for
looping, procedure calls and alternation (therefore, MASM is an example of a high-
level assembler). Later versions added the capability of producing programs for the
Windows operating systems that were released to follow on from MS-DOS. MASM
is one of the few Microsoft development tools (another was NMAKE) for which one
version targets both 16-bit and 32-bit. Early version were MS-DOS applications.
Later versions also were OS/2 applications (versions 5.1 and 6.0) and later versions
after that (versions 6.1+) were Win32 console applications (initially (in versions 6.1
and 6.11) with the Phar Lap TNT DOS extender included to run these versions of
MS-DOS). However see Phar Lap (company) for the whole debacle that cause early
versions that were Win32 console applications (version 6.1) to fail to run on final
versions of Windows NT.
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MIL Manual
Testing:
C:\masm61\bin\>MASM sample.asm
C:\masm61\bin\>LINK sample.obj
C:\masm61\bin\>EXE2BIN sample sample.com
Sample output:
C:\MASM611>ml assgn1.asm
Microsoft (R) Macro Assembler Version 6.11
Copyright (C) Microsoft Corp 1981-1993. All rights reserved.
Assembling: assgn1.asm
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C:\MASM611>assgn1
Addition:60
C:\MASM611>
Conclusion:
ALP to add ‘N’ numbers is written, compiled and executed successfully.
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MIL Manual
ASSIGNMENT No: 2
Title of Assignment: Write an ALP in 8086 to count Odd and Even nos. from the array
stored in Memory
Relevant Theory:
The Header
• The header contains various directives which do not produce machine code
• Sample header:
Equates
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Count EQU 10
Element EQU 5
Size = Count * Element
MyString EQU "Maze of twisty passages"
Size = 0
.data
numRows DB 25
numColumns DB ?
videoBase DW 0800h
aTOm DB "ABCDEFGHIJKLM"
Program Data and Storage
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Defining Data
DW 40Ch,10b,-13,0
DB 255,?,-128,'X'
ANum DB -4
DW 17
ONE
UNO DW 1
X DD ?
Arrays
• Any consecutive storage locations of the same size can be called an array
X DW 040Ch,10b,-13,0
Y DB 'This is an array'
Z DD -109236, FFFFFFFFh, -1, 100b
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DUP
DB 40 DUP(?)
DW 10h DUP(0)
DB 3 DUP("ABC")
DB 4 DUP(3 DUP (0,1), 2 DUP('$'))
Word Storage
• Word, doubleword, and quadword data are stored in reverse byte order (in
memory)
An example
Label Mnemonic Operand Comment
---------------------------------------------------------
.data
exCode DB 0 ;A byte variable
myWord DW ? ;Uninitialized word var.
.code
MAIN:
mov ax,@data ;Initialize DS to address
mov ds,ax ; of data segment
jmp Exit ;Jump to Exit label
mov cx,10 ;This line skipped!
Exit: mov ah,04Ch ;DOS function: Exit prog
mov al, exCode ;Return exit code value
int 21h ;Call DOS. Terminate prog
END MAIN ;End Program and specify entry point
• Labels mark places in a program which other instructions and directives reference
• Labels in the code segment always end with a colon
• Labels in the data segment never end with a colon
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• Labels can be from 1 to 31 characters long and may consist of letters, digits, and
the special characters ? . @ _ $ %
• If a period is used, it must be the first character
• Labels must not begin with a digit
• The assembler is case insensitive
• For an instruction, the operand field specifies the data that are to be acted on by
the instruction. May have zero, one, or two operands
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;
; Initialize registers
;
MOV AX,0
MOV BX,0
The Closing
• END is a pseudo-op; the single "operand" is the label specifying the beginning of
execution, usually the first instruction after the .code pseudo-op
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Algorithm:
Testing:
Sample Output:
C:\DOCUME~1\MAE>cd\
C:\>cd masm611
C:\MASM611>ml assgn2.asm
Microsoft (R) Macro Assembler Version 6.11
Copyright (C) Microsoft Corp 1981-1993. All rights reserved.
Assembling: assgn2.asm
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Libraries [.lib]:
Definitions File [nul.def]:
LINK : warning L4038: program has no starting address
C:\MASM611>assgn2
Even Nos:
10
12
14
C:\MASM611>
Conclusion:
All the odd and even numbers are correctly classified and displayed.
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ASSIGNMENT No: 3
Title of Assignment: Write an ALP in 8086 to find and count Negative nos. from the
array of signed nos. stored in Memory
Relevant Theory:
Signed numbers: (sign-magnitude notation) in computers is the use of the high-order bit
(left end) of a binary word to represent the numeric sign: 0 for + and 1 for - followed by a
binary number that is an absolute magnitude or a two's complement of an absolute
magnitude. For example, 01001 means plus 9. In 2's complement: 11101 means minus 3
and 10111 means minus 9.
00000000 0 0
00000001 1 1
10000000 −0 128
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Testing:
Sample Output:
C:\MASM611>ml assgn3.asm
Microsoft (R) Macro Assembler Version 6.11
Copyright (C) Microsoft Corp 1981-1993. All rights reserved.
Assembling: assgn3.asm
C:\MASM611>assgn3
The Nos in memory:
10
111
12
13
144
Positive Nos:
10
111
12
13
C:\MASM611>
Conclusion:
All the odd and even numbers are correctly classified and displayed.
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ASSIGNMENT No: 4
Relevant Theory:
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Model definition
•.MODEL SMALL
–Most widely used memory model.
–The code must fit in 64k.
–The data must fit in 64k.
•.MODEL MEDIUM
–The code can exceed 64k.
–The data must fit in 64k.
•.MODEL COMPACT
–The code must fit in 64k.
–The data can exceed 64k.
•MEDIUM and COMPACT are opposites.
Algorithm:
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Testing:
Sample Output:
C:\MASM611>ml assgn4.asm
Microsoft (R) Macro Assembler Version 6.11
Copyright (C) Microsoft Corp 1981-1993. All rights reserved.
Assembling: assgn4.asm
C:\MASM611>assgn4
Enter no:05
It is a Prime Number!!!
Factorial = 120
C:\MASM611>
Conclusion:
Factorial of the number is calculated and displayed. The number is classified as a prime
or not successfully.
ASSIGNMENT No: 5
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Title of Assignment: Write an ALP in 8086 to find the Largest No. in a given Array.
Relevant Theory:
CMP Instruction
� CMP operand1,operand2
� operand1 - operand2
� Flags are updated and the result is discarded.
� CMP AL,BL
� CMP BX,0ABCH
� CMP DL,[BX]
Conditional Transfers
� Used with unsigned integers
� JA/JNBE – Jump if above – Z=0 and C=0
� JAE/JNB – Jump if above or equal – C=0
� JB/JNA – Jump if below – C=1
� JBE/JNA – Jump if below or equal – Z=1 and C=1
� CMP AL,BL
� JA NEXT
� MOV CL,0
� .
� .
� NEXT:
� Other conditions
� JE/JZ – Jump if equal – Z=1
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Algorithm:
Assume: numbers are stored in the memory
Maintain a temporary storage space say temp
Compare first two numbers
Store larger number in temp
Compare next pair of numbers and maintain the largest number in temp
Display all the numbers and the largest number.
Testing:
Sample Output:
C:\DOCUME~1\MAE>cd\
C:\>cd masm611
C:\MASM611>ml assgn5.asm
Microsoft (R) Macro Assembler Version 6.11
Copyright (C) Microsoft Corp 1981-1993. All rights reserved.
Assembling: assgn5.asm
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C:\MASM611>assgn5
Nos in array:
0015
0005
000D
00FF
0011
00EF
Largest No:
00FF
C:\MASM611>
Conclusion:
Largest number is found and displayed.
ASSIGNMENT No: 6
Title of Assignment: Write an ALP in 8086 to convert 4-digit Hex No. To BCD No. and
vice versa
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Relevant Theory:
To BCD-encode a decimal number using the common encoding, each decimal digit is
stored in a four-bit nibble.
Decimal: 0 1 2 3 4 5 6 7 8 9
BCD: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001
Thus, the BCD encoding for the number 127 would be:
Since most computers store data in eight-bit bytes, there are two common ways of storing
four-bit BCD digits in those bytes:
• each digit is stored in one byte, and the other four bits are then set to all zeros, all
ones (as in the EBCDIC code), or to 0011 (as in the ASCII code)
• two digits are stored in each byte.
Unlike binary encoded numbers, BCD encoded numbers can easily be displayed by
mapping each of the nibbles to a different character. Converting a binary encoded number
to decimal for display is much harder involving integer multiplication or divide
operations. The BIOS in many PCs keeps the date and time in BCD format, probably for
historical reasons (it avoided the need for binary to ASCII conversion).
Algorithm:
Make a user friendly menu
Accept a BCD number
Convert into its Hex equivalent and display result
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Testing:
Sample Output:
C:\MASM611>ml assgn6.asm
Microsoft (R) Macro Assembler Version 6.11
Copyright (C) Microsoft Corp 1981-1993. All rights reserved.
Assembling: assgn6.asm
C:\MASM611>assgn6
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Conclusion:
BCD-Hex and Hex-BCD conversion is successfully implemented.
ASSIGNMENT No: 7
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Bubble sort is a simple sorting algorithm. It works by repeatedly stepping through the
list to be sorted, comparing two items at a time and swapping them if they are in the
wrong order. The pass through the list is repeated until no swaps are needed, which
means the list is sorted. The algorithm gets its name from the way smaller elements
"bubble" to the top (i.e. the beginning) of the list via the swaps. Because it only uses
comparisons to operate on elements, it is a comparison sort. This is the easiest
comparison sort to implement.
Algorithm:
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end for
end procedure
Testing:
Sample Output:
C:\MASM611>ml assgn7.asm
Microsoft (R) Macro Assembler Version 6.11
Copyright (C) Microsoft Corp 1981-1993. All rights reserved.
Assembling: assgn7.asm
C:\MASM611>assgn7
C:\MASM611>assgn7
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12
11
10
C:\MASM611>
Conclusion:
Bubble sort method is successfully implemented for sorting the numbers in ascending as
well as descending order.
ASSIGNMENT No: 8
Title of Assignment: Write an ALP in 8086 to convert a string entered from Keyboard
from Lower Case to Upper Case and vice versa
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Relevant Theory:
ASCII Table:
Algorithm:
Accept the string from user
Accepted string will be in its ASCII equivalent form
Find capital letters by checking the bounds of 41h-5Ah for their ASCII Hex equivalents
Add 20h to get their equivalent small letters
Find small letters by checking the bounds of 61h-7Ah for their ASCII Hex equivalents
Subtract 20h to get their equivalent capital letters
Display the results and exit
Testing:
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Sample Output:
C:\MASM611>ml assgn8.asm
Microsoft (R) Macro Assembler Version 6.11
Copyright (C) Microsoft Corp 1981-1993. All rights reserved.
Assembling: assgn8.asm
C:\MASM611>assgn8
C:\MASM611>
Conclusion:
An 8086 ALP to swap capital and small letters is successfully implemented.
ASSIGNMENT No: 9
Title of Assignment: Write your own Interrupt Service Routine to handle INT-4
Overflow OR Write your own Interrupt Service Routine to handle INT-0 Divide Error
Relevant Theory:
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The Interrupt Descriptor Table (IDT) is a data structure used by the x86 architecture to
implement an interrupt vector table. The IDT is used by the processor to determine the
correct response to interrupts and exceptions.
Use of the IDT is triggered by three types of events: hardware interrupts, software
interrupts, and processor exceptions, which together are referred to as "interrupts". The
IDT consists of 256 interrupt vectors.
Interrupt Table
Interrupt Description
INT 00h CPU: Division by Zero
INT 01h CPU: Single Step for debugging
INT 02h CPU: NMI, used e.g. by POST for memory errors
INT 03h CPU: Breakpoint for debugging
INT 04h CPU: Numeric Overflow
INT 05h Print Screen
INT 08h IRQ0: Called by system timer 18.2 times per second
INT 09h IRQ1: Called by keyboard
INT 0Bh IRQ3: Called by 2nd serial port COM2
INT 0Ch IRQ4: Called by 1st serial port COM1
IRQ5: Called by hard disk controller (PC/XT) or 2nd parallel port
INT 0Dh
LPT2 (AT)
INT 0Eh IRQ6: Called by floppy disk controller
INT 0Fh IRQ7: Called by 1st parallel port LPT1 (printer)
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Algorithm:
Write your own ISR
Store the original address of that ISR from IVT into a variable
Replace the original address on IVT with your sub-routine
Simulate a condition to activate your ISR
Restore back the original address at appropriate location in IVT
Verify the results
Testing:
Sample Output:
C:\MASM611>ml assgn9.asm
Microsoft (R) Macro Assembler Version 6.11
Copyright (C) Microsoft Corp 1981-1993. All rights reserved.
Assembling: assgn9.asm
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C:\MASM611>assgn9
Conclusion:
The ISR is written and successfully run by making appropriate changes in the IVT and
simulating related situations.
ASSIGNMENT No: 10
Relevant Theory:
The most familiar palindromes, in English at least, are character-by-character: the written
characters read the same backwards as forwards. Palindromes may consist of a single
word (such as “civic” or “level” ), a phrase or sentence (“Neil, a trap! Sid is part alien!”,
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"Was it a rat I saw?") or a longer passage of text (“Sit on a potato pan, Otis.”) Spaces,
punctuation and case are usually ignored.
String Instructions
LODS/LODSB/
LODSW/LODSD
•Loads the AL, AX or EAX registers with the content of the memory
byte, word or double word pointed to by SI relative to DS. After the
transfer is made, the SI register is automatically updated as follows:
–SI is incremented if DF=0.
–SI is decremented if DF=1.
LODS/LODSB/
LODSW/LODSD
•Examples:
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–LODSB
AL=DS:[SI]; SI=SI ±1
–LODSW
AX=DS:[SI]; SI=SI ±2
–LODSD
EAX=DS:[SI]; SI=SI ±4
–LODS MEAN
AL=DS:[SI]; SI=SI ±1 (if MEAN is a byte)
–LODS LIST
AX=DS:[SI]; SI=SI ±2(if LIST is a word)
–LODS MAX
EAX=DS:[SI]; SI=SI ±4(if MAX is a double word)
LODS/LODSB/
LODSW/LODSDExampleAssume:LocationContentRegister
SI500HMemory location 500H'A'Register AL'2'After execution of
LODSBIf DF=0 then:LocationContentRegister SI501HMemory location
500H'A'Register AL'A'Else if DF=1 then:LocationContentRegister
SI4FFHMemory location 500H'A'Register AL'A'
STOS/STOSB/
STOSW/STOSD
STOS/STOSB/
STOSW/STOSD
•Examples:
–STOSB
ES:[DI]=AL; DI=DI ±1
–STOSW
ES:[DI]=AX; DI=DI ±2
–STOSD
ES:[DI]=EAX; DI=DI ±4
–STOS MEAN
ES:[DI]=AL; DI=DI ±1 (if MEAN is a byte)
–STOS LIST
ES:[DI]=AX; DI=DI ±2(if LIST is a word)
–STOS MAX
ES:[DI]=EAX; DI=DI ±4(if MAX is a double word)
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STOS/STOSB/
STOSW/STOSDExampleAssume:LocationContentRegister
DI500HMemory location 500H'A'Register AL'2'After execution of
STOSBIf DF=0 then:LocationContentRegister DI501HMemory location
500H'2'Register AL'2'Else if DF=1 then:LocationContentRegister
DI4FFHMemory location 500H'2'Register AL'2'
MOVS/MOVSB/
MOVSW/MOVSD
•Transfers the contents of the the memory byte, word or double word
pointed to by SI relative to DS to the memory byte, word or double
word pointed to by DI relative to ES. After the transfer is made, the DI
register is automatically updated as follows:
–DI is incremented if DF=0.
–DI is decremented if DF=1.
MOVS/MOVSB/
MOVSW/MOVSD
•Examples:
–MOVSB
ES:[DI]=DS:[SI]; DI=DI ±1;SI=SI ±1
–MOVSW
ES:[DI]= DS:[SI]; DI=DI ±2; SI=SI ±2
–MOVSD
ES:[DI]=DS:[SI]; DI=DI ±4; SI=SI ±4
–MOVS MEAN
ES:[DI]=DS:[SI]; DI=DI ±1; SI=SI ±1 (if MEAN is a byte)
–MOVS LIST
ES:[DI]=DS:[SI]; DI=DI ±2; SI=SI ±2(if LIST is a word)
–MOVS MAX
ES:[DI]=DS:[SI]; DI=DI ±4; SI=SI ±4(if MAX is a double word)
MOVS/MOVSB/
MOVSW/MOVSDExampleAssume:LocationContentRegister
SI500HRegister DI600HMemory location 500H'2'Memory location
600H'W'After execution of MOVSBIf DF=0
then:LocationContentRegister SI501HRegister DI601HMemory location
500H'2'Memory location 600H'2'Else if DF=1
then:LocationContentRegister SI4FFHRegister DI5FFHMemory location
500H'2'Memory location 600H'2'
CMPS/CMPSB/
CMPSW/CMPSD
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•Compares the contents of the the memory byte, word or double word
pointed to by SI relative to DS to the memory byte, word or double
word pointed to by DI relative to ES and changes the flags accordingly.
After the comparison is made, the DI and SI registers are automatically
updated as follows:
–DI and SI are incremented if DF=0.
–DI and SI are decremented if DF=1
SCAS/SCASB/
SCASW/SCASD
•Compares the contents of the AL, AX or EAX register with the memory
byte, word or double word pointed to by DI relative to ES and changes
the flags accordingly. After the comparison is made, the DI register is
automatically updated as follows:
–DI is incremented if DF=0.
–DI is decremented if DF=1.
Algorithm:
Prepare a user friendly menu
Accept a string from user
Calculate the length and display
Reverse the string and display
Check if palindrome and display
Exit when user selects that option
Testing:
Sample Output:
C:\MASM611>ml assgn10.asm
Microsoft (R) Macro Assembler Version 6.11
Copyright (C) Microsoft Corp 1981-1993. All rights reserved.
Assembling: assgn10.asm
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MIL Manual
C:\MASM611>assgn10
2) Length of String
3) Reverse String
4) Check Palindrome
5) Exit
2) Length of String
3) Reverse String
4) Check Palindrome
5) Exit
2) Length of String
3) Reverse String
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4) Check Palindrome
5) Exit
2) Length of String
3) Reverse String
4) Check Palindrome
5) Exit
2) Length of String
3) Reverse String
4) Check Palindrome
5) Exit
Conclusion: String is accepted and its length the calculated. The string is reversed and
checked for palindrome. All the results are displayed.
ASSIGNMENT No: 11
Title of Assignment: Write an ALP in 8086 to find no. of words, characters, lines &
capital letters from given text and no. of occurrences of sub-string in Data Segment
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Relevant Theory:
ASCII Table:
Note ASCII values of Enter (cr) = 13 and space = 32 to take into account words and
lines.
Algorithm:
Prepare a user friendly menu
Assume the string is stored in the memory
Calculate total number of characters
Calculate total no of words by counting spaces (ASCII equ = 32)
Calculate total no of lines by counting crs (ASCII eqn = 13)
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Calculate total capital characters using Hex equivalent ASCII bound of 41h-5Ah
Calculate sub-string occurrences using DI and SI as pointers.
Display all the results
Testing:
Sample Output:
C:\MASM611>assgn11
Assembling: assgn11a.asm
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C:\MASM611>assgn11a
Conclusion:
From the given string total characters, capital letters, words and lines are accurately
calculated. Occurrence of sub-strings is successfully implemented.
ASSIGNMENT No: 12
Title of Assignment: Write an ALP in 8086 to perform String manipulation using FAR
Procedure to Concatenate & Compare two strings.
Note: Use PUBLIC & EXTERN directive. Create .OBJ files and link them to create an
EXE file
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Relevant Theory:
Procedures
� Also known as subroutines, these sets of
instructions usually perform a single task.
� They are reusable code, that can be
executed as often as needed by calling it.
� Procedures save memory, but the calling
of a procedure takes a small amount of
time.
� Format
� Name PROC [NEAR or FAR]
� Subroutine code
� RET
� ENDP
� Global procedures are defined as FAR.
� Local procedures are defined as NEAR.
� CALL destination
� Calls a subroutine at location destination.
� Different addressing modes may be used for
destination.
� CALL DELAY
� CALL EBX
� CALL ARRAY[BX]
� RET
� Returns execution of program to location
stored in stack.
� NEAR or FAR is dependent on procedure
definition.
Technically, the include directive provides you with all the facilities you need to create modular
programs. You can build up a library of modules, each containing some specific routine, and
include any necessary modules into an assembly language program using the appropriate
include commands. MASM (and the accompanying LINK program) provides a better way:
external and public symbols.
One major problem with the include mechanism is that once you've debugged a routine,
including it into an assembly wastes a lot of time since MASM must reassemble bug-free code
every time you assemble the main program. A much better solution would be to preassemble the
debugged modules and link the object code modules together rather than reassembling the entire
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program every time you change a single module. This is what the public and extern
directives provide for you. Extrn is an older directive that is a synonym for extern. It provides
compatibility with old source files. You should always use the extern directive in new source
code.
To use the public and extern facilities, you must create at least two source files. One file
contains a set of variables and procedures used by the second. The second file uses those
variables and procedures without knowing how they're implemented. To demonstrate, consider
the following two modules:
;Module #1:
;Module #2:
extern Var1:word, Var2:word, Proc1:near
CSEG segment para public 'code'
.
.
.
mov Var1, 2
mov Var2, 3
call Proc1
.
.
.
CSEG ends
end
Module #2 references Var1, Var2, and Proc1, yet these symbols are external to module #2.
Therefore, you must declare them external with the extern directive. This directive takes the
following form:
Name is the name of the external symbol, and type is the type of that symbol. Type may be any
of near, far, proc, byte, word, dword, qword, tbyte, abs (absolute, which is a
constant), or some other user defined type.
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The current module uses this type declaration. Neither MASM nor the linker checks the declared
type against the module defining name to see if the types agree. Therefore, you must exercise
caution when defining external symbols. The public directive lets you export a symbol's value
to external modules. A public declaration takes the form:
Each symbol appearing in the operand field of the public statement is available as an external
symbol to another module. Likewise, all external symbols within a module must appear within a
public statement in some other module.
Once you create the source modules, you should assemble the file containing the public
declarations first. With MASM 6.x, you would use a command like
ML /c pubs.asm
The "/c" option tells MASM to perform a "compile-only" assembly. That is, it will not try to link the
code after a successful assembly. This produces a "pubs.obj" object module.
Next, assemble the file containing the external definitions and link in the code using the MASM
command:
ML exts.asm pubs.obj
Assuming there are no errors, this will produce a file "exts.exe" which is the linked and executable
form of the program.
Note that the extern directive defines a symbol in your source file. Any attempt to redefine that
symbol elsewhere in your program will produce a "duplicate symbol" error. This, as it turns out, is
the source of problems which Microsoft solved with the externdef directive.
Algorithm:
1. Accept the first string
2. Accept the second string
3. Call the far procedure to concatenate the strings
4. Maintain the stack pointer
5. Call the far procedure to compare the strings
6. Maintain the stack pointer
7. Display the results and exit
Testing:
Sample Output:
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Assembling: assgn12.asm
C:\MASM611>masm pcon.asm
Microsoft (R) MASM Compatibility Driver
Copyright (C) Microsoft Corp 1993. All rights reserved.
Assembling: pcon.asm
C:\MASM611>masm pcmp.asm
Microsoft (R) MASM Compatibility Driver
Copyright (C) Microsoft Corp 1993. All rights reserved.
Assembling: pcmp.asm
C:\MASM611>link assgn12+pcon+pcmp
C:\MASM611>assgn12
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Concatenated string:microprocessor
Conclusion:
String concatenation and comparison successfully implemented using far procedures.
ASSIGNMENT No: 13
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Relevant Theory:
Study Apparatus:
DYNA-86: (8086-SDK board)
DYNA-8255 study card
DYNA 86 Specifications:
Microprocessors: 8086, operating frequency: 8 MHz
64 KB ROM with monitor firmware (in two 27256—U30 and U32)
64 KB battery backed static RAM (in two 62256—U31 and U33)
Support chips: 8254, 8251, 8259, 8255, 8279, socket for 8087
Memory Map:
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Port A: 30h
Port B: 31h
Port C: 32h
CWR : 33h
There are three modes used for parallel data transfer from 8086 Microprocessor to output
devices and from input devices to 8086 Microprocessor. These are
1. Simple Input and Output
2. Simple strobe I/O
3. a. Single handshake I/O
b. Double handshake I/O
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raises STB signal high to indicate that valid data is present on the data lines. After the
data is read in by the receiving device it drops its ACK signal to indicate that data on the
data lines are read successfully.
Mode Selection
There are three basic modes of operation than can be selected by the system software:
Mode 0 - Basic Input/Output
Mode 1 - Strobed Input/Output
Mode 2 - Bi-directional Bus
The modes for Port A and Port B can be separately defined, while Port C is divided into
two portions as required by the Port A and Port B definitions.
I/O MODE
STB - Strobe Input : A “low” on this input loads data into the input latch.
IBF - Input Buffer Full : A “high” on this output indicates that the data has been loaded
into the input latch.
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INTR - Interrupt Request : A “high” on this output can be used to interrupt the CPU
when input device is requesting service.
OBF - Output Buffer Full : The OBF output will go “low” to indicate that the CPU has
written data out to be specified port.
ACK - Acknowledge Input: A “low” on this input informs the 8255 that the data from
Port A or Port B is ready to be accepted.
INTR - Interrupt Request: A “high” on this output can be used to interrupt the CPU
when an output device has accepted data transmitted by the CPU.
Sample Programs:
(I) Out 0AH on port A: Configure 8255 in mode 0. See the status of port A by
observing LEDs.
A 0100:0000
MOV AL,80
OUT 33,AL
MOV AL,0A
OUT 30,AL
INT 3
G 0100:0000
(II) Configure 8255 in mode 0, porst A-B-C as i/ps, read data in different
registers. The i/ps are given to the ports by grounding various port lines to
ground, using the TAB connectors. Observe the contents of the registers using
command R.
A 0100:0000
MOV AL,9B
OUT 33,AL
IN AL,30
MOV BL,AL
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IN AL,31
MOV CL,AL
INT 3
G 0100:0000
Testing:
For the various programs verify the output by observing the bits of the corresponding
ports, which is demonstrated by the associated LEDs.
Conclusion:
8255 is initialized in an I/O mode and experiments are performed on all the three ports.
ASSIGNMENT No: 14
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Title of Assignment: Write an ALP in 8086 to initialize 8255 in BSR Mode. Set & Reset
Bits 1,3 & 5 after every 2 Seconds. Draw block diagram of 8255 & show the interfacing
details with 8086
Relevant Theory:
Study Apparatus:
DYNA-86: (8086-SDK board)
DYNA-8255 study card
DYNA 86 Specifications:
Microprocessors: 8086, operating frequency: 8 MHz
64 KB ROM with monitor firmware (in two 27256—U30 and U32)
64 KB battery backed static RAM (in two 62256—U31 and U33)
Support chips: 8254, 8251, 8259, 8255, 8279, socket for 8087
Memory Map:
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Trace T[[seg:]strt]
Go G[[[seg:]strt],[[seg:]brk]]
Hex to Dec HDnum
Dec to Hex Dhnum
Load file L[seg:]
Write file W[seg:],strt,end
Input from port IN[W]addr
Output to port O[W]addr,[byte/word]
Assemble A[[seg:]off]
Unassemble U[[seg:]off[,[seg:]off]]
Port A: 30h
Port B: 31h
Port C: 32h
CWR : 33h
There are three modes used for parallel data transfer from 8086 Microprocessor to output
devices and from input devices to 8086 Microprocessor. These are
1. Simple Input and Output
2. Simple strobe I/O
3. a. Single handshake I/O
b. Double handshake I/O
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raises STB signal high to indicate that valid data is present on the data lines. After the
data is read in by the receiving device it drops its ACK signal to indicate that data on the
data lines are read successfully.
Mode Selection
There are three basic modes of operation than can be selected by the system software:
Mode 0 - Basic Input/Output
Mode 1 - Strobed Input/Output
Mode 2 - Bi-directional Bus
The modes for Port A and Port B can be separately defined, while Port C is divided into
two portions as required by the Port A and Port B definitions.
BSR MODE:
STB - Strobe Input : A “low” on this input loads data into the input latch.
IBF - Input Buffer Full : A “high” on this output indicates that the data has been loaded
into the input latch.
INTR - Interrupt Request : A “high” on this output can be used to interrupt the CPU
when input device is requesting service.
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OBF - Output Buffer Full : The OBF output will go “low” to indicate that the CPU has
written data out to be specified port.
ACK - Acknowledge Input: A “low” on this input informs the 8255 that the data from
Port A or Port B is ready to be accepted.
INTR - Interrupt Request: A “high” on this output can be used to interrupt the CPU
when an output device has accepted data transmitted by the CPU.
Sample Programs:
To set/reset bits of port C. After configuring Port C as o/p port, individual bits
of port C can be set/reset in this mode.
A 0100:0000
MOV AL,80
OUT 33,AL
go: MOV AL,01
OUT 33,AL
CALL 0040 -- Address of the delay routine
MOV AL,00
OUT 33,AL
CALL 0040
JMP go
INT 3
G 0100:0000
Delay Routine:
A 0100:0040
MOV BX,0A
l1: MOV CX,DA00
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l2: DEC CX
JNZ l2
DEC BX
JNZ l1
RET
Testing:
For the BSR programs verify the output by observing the bits of port C. Observed the
port C LEDs getting turned ON and OFF as bits are getting set and reset
Conclusion:
8255 is initialized in an BSR mode and experiments are performed on port C.
ASSIGNMENT No: 15
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Relevant Theory:
Study Apparatus:
DYNA-86: (8086-SDK board)
DYNA-8253 study card
DYNA 86 Specifications:
Microprocessors: 8086, operating frequency: 8 MHz
64 KB ROM with monitor firmware (in two 27256—U30 and U32)
64 KB battery backed static RAM (in two 62256—U31 and U33)
Support chips: 8254, 8251, 8259, 8255, 8279, socket for 8087
Memory Map:
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Counter 0: 30h
Counter 1: 31h
Counter 2: 32h
CWR : 33h
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8253 is a programmable Interval timer/counter specifically designed for use with the Intel
Micro computer systems. It is used for generation of accurate time delay under software
control. User initializes one of the counters of the 8253 with the desired quantity, then
upon command the 8253 will count-out the delay and interrupt the CPU when it has
completed its tasks.
Sr No Mode 0 Status
01 After count is loaded , Output Goes Low
02 When TC (Termination Cnt) is reached High
03 GATE is HIGH Starts Counting
04 GATE is LOW Stops Counting
05 GATE RISING Pulse No Change
06 New Count is loaded in between Starts with new count
Sr No Mode 1 Status
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Sr Mode 2 Status
No
01 After count is loaded , Output High
Goes
02 When TC is reached Low for one period of input clock
03 GATE is HIGH Starts Counting
04 GATE is LOW Stops Counting
05 GATE RISING Pulse Starts Counting by reloading count value
again
06 New Count is loaded in between No Effect
Sr Mode 3 Status
No
01 GATE is Starts Counting
HIGH
02 GATE is Stops Counting
LOW
03 GATE No Effect
RISING Pulse
04 New Count is No Effect
loaded in
between
Special output will remain high until one half the count has been
Feature completed (for even numbers) and go low for the other half of
the count. If the count is odd, the output will be high for
(N+1)/2 counts and low for (N-1)/2 counts.
Sr Mode 4 Status
No
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Sr Mode 5 Status
No
01 After count is loaded , Output High
Goes
02 When TC is reached Low for one period of input clock
03 GATE is HIGH No Effect
04 GATE is LOW No Effect
05 GATE RISING Pulse Initiates Counting
06 New Count is loaded in between Starts Counting by reloading count value
again
Special Feature Repeat Process again
Mode 0
A 0100:0000
MOV AL,11
OUT 33,AL
MOV AL,04 (COUNT VALUE)
OUT 30,AL
INT 3
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Testing:
Conclusion:
8253 is successfully interfaced with 8086 system. 8253 is configured in all the six modes
and the output is observed with the help of the respective LEDs.
ASSIGNMENT No: 16
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Title of Assignment: Write an ALP in 8086 to initialize 8279 in Display mode for
scrolling display.
• Initialize 8279 in 8*8 bit character display, Left Entry Decoded Mode.
• Initialize 8279 in 16*8 bit character display, Right Entry Encoded Mode.
Draw the block diagram of 8279 & show the interfacing details with 8086
Relevant Theory:
Study Apparatus:
DYNA-86: (8086-SDK board)
DYNA-8279 study card
DYNA 86 Specifications:
Microprocessors: 8086, operating frequency: 8 MHz
64 KB ROM with monitor firmware (in two 27256—U30 and U32)
64 KB battery backed static RAM (in two 62256—U31 and U33)
Support chips: 8254, 8251, 8259, 8255, 8279, socket for 8087
Memory Map:
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SYMBOL DESCRIPTION
DB0-DB7 BI-DIRECTIONAL DATA BUS: All data and commands between the
CPU
and 8279 are transmitted on these lines.
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RESET A high signal on this pin resets the 8279. After being reset the 8279 is
placed in 16 8-bit character display-left entry and Encoded scan
keyboard-2 key lockout. Along with this the program clock prescaler is
set to 31.
A0 A high on this line indicates the signals in or out are interpreted as a
command or status. A low indicates that they are data.
IRQ In a keyboard mode, the interrupt line is high when there is data in the
FIFO/Sensor RAM. The interrupt line goes low with each FIFO/Sensor
RAM read and returns high if there is still information in the RAM. In a
sensor mode, the interrupt line goes high whenever a change in a sensor is
detected.
SL0-SL3 Scan lines, which are used to scan the key switch or sensor matrix and
display digits. These lines can be either encoded (1 of 16) or decoded (1
of 4).
RL0-RL7 Return line inputs which are connected to the scan lines through the keys
or sensor switches. They have active internal pull-ups to keep them high
until a switch closure pulls one low. They also serve as 8-bit Input in
Strobed Input Mode.
SHIFT The shift input status is stored along with the key position on key closure
in the Scanned Keyboard modes.
CNTL/STB For keyboard mode this line is used as a control input and stored like
status on a key closure. The line is also the strobe line that enters the data
into the FIFO in the strobed input mode. (Rising Edge).
OUT A0-A3 These two ports are the outputs for the 16x4 display refresh registers. The
OUT B0-B3 data from these outputs is synchronized to the scan lines (SL0 – SL3) for
multiplexed digit displays. The two 4-bit ports may be blanked
independently and considered as one 8-bit port.
BD This output is used to blank the display during digit switching or by a
display blanking command.
The Intel 8279 is a general purpose Programmable Keyboard and Display I/O Interface
device designed for use with Intel Microprocessors.
The 8279 has two sections: keyboard and display. CPU is relieved from scanning the
keyboard or refreshing the display.
1) The Keyboard portion can provide a scanned interface to a 64-contact key
matrix.
The keyboard section will also interface to regular typewriter style keyboards
or random toggle or thumb switches, array of Sensors or Strobed Interface
Keyboards.
Key depressions can be 2-key lockout or N-key rollover.
Keyboard entries are debounced and strobed in an 8-char FIFO.
2) The display portion provides a scanned display interface for LED,
incandescent and other popular display technologies. Both numeric and
alphanumeric segment displays may be used.
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Input Modes
1. Scanned Keyboard-with encoded (8 x 8 key keyboard) or decoded (4 x 8 key
keyboard) scan lines. A key depression generates a 6-bit encoding of key position.
Position and shift and control status are stored in the FIFO.
2. Scanned Sensor Matrix-with encoded (8 x 8 matrix switches) or decoded (4 x 8
matrix switches) scan lines. Key status (open or closed) stored in RAM addressable by
CPU.
3. Strobed Input-Data on return lines during control line strobe is transferred to FIFO.
Output Modes
1. 8 or 16 character-multiplexed displays that can be organized as dual 4-bit or single 8
bit
2. Right entry or left entry display formats.
Scan Counter: The scan counter has two modes. In the encoded mode, the counter
provides a binary count that must be externally decoded to provide the scan lines for the
keyboard and display. In the decoded mode, the scan counter decodes the least significant
2 bits and provides a decoded 1 of 4 scan.
In the Encoded mode, the scan lines are active high outputs.
In the Decoded mode, the scan lines are active low outputs.
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3. In Strobed input mode, the contents of the return lines are transferred to the FIFO on
the rising edge of the CNTL/STB line pulse.
The following commands program the 8279 operating modes. The commands are
sent on the Data Bus with CS low and A0 is high and are loaded to the 8279 on the rising
edge of WR.
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Left Entry : Left Entry mode is the simplest display format in that each display position
directly corresponds to a byte (or nibble) in the Display RAM. Address 0 in the RAM is
the left-most display character and address 15 (or address 7 In 8 character display) is the
right most display character.
Right Entry : Right entry is the method used by most electronic calculators. The first
entry is placed in the right most display character. The next entry is also placed in the
right most character after the display is shifted left one character.
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FlFO status is used in the Keyboard and Strobed Input modes to indicate the number of
characters in the FIFO and to indicate whether an error has occurred. There are two types
of errors possible: overrun and under run. Overrun occurs when the entry of another
character into a full FlFO is attempted. Under run occurs when the CPU tries to read an
empty FIFO. The FlFO status word also has a bit to indicate that the Display RAM was
unavailable because a Clear Display or Clear All command had not completed its
clearing operation. In Special Error Mode the S/E bit is showing the error flag and serves
as an indication to whether a simultaneous multiple closure error has occurred.
DU S/E O U F N N N
SAMPLE CODES :
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A 0100 :0000
A 0100 :0040
MOV SI,0A
L1 : MOV DI,DA00
L2 : DEC CX
JNZ L2
DEC BX
JNZ L1
RET
E 0100 :0030
0030 : 7 E
0031 : 4 6
0032 : E 6
0033 : E C
A 0100 :0000
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OUT 31,AL
MOV CL,10
MOV AX,CS
MOV DS,AX
MOV BX,0030
Go : MOV AL,[BX]
OUT 30,AL
CALL 0040
INC BX
DEC CL
JNZ Go
JMP back
INT 3
A 0100 :0040
MOV SI,0A
L1 : MOV DI,DA00
L2 : DEC CX
JNZ L2
DEC BX
JNZ L1
RET
E 0100 :0030
0030 : 7 E
0031 : 4 6
0032 : E 6
0033 : E C…….add 16 character codes.
Testing:
Observe the display. Verify the left and right entry of the display characters.
Conclusion:
8279 successfully interfaced with 8086 system. The decoded and encoded modes for
displaying information are implemented.
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ASSIGNMENT No: 17
Relevant Theory:
Study Apparatus:
DYNA-86: (8086-SDK board)
DYNA-8279 study card
DYNA 86 Specifications:
Microprocessors: 8086, operating frequency: 8 MHz
64 KB ROM with monitor firmware (in two 27256—U30 and U32)
64 KB battery backed static RAM (in two 62256—U31 and U33)
Support chips: 8254, 8251, 8259, 8255, 8279, socket for 8087
Memory Map:
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SYMBOL DESCRIPTION
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DB0-DB7 BI-DIRECTIONAL DATA BUS: All data and commands between the
CPU
and 8279 are transmitted on these lines.
RESET A high signal on this pin resets the 8279. After being reset the 8279 is
placed in 16 8-bit character display-left entry and Encoded scan
keyboard-2 key lockout. Along with this the program clock prescaler is
set to 31.
A0 A high on this line indicates the signals in or out are interpreted as a
command or status. A low indicates that they are data.
IRQ In a keyboard mode, the interrupt line is high when there is data in the
FIFO/Sensor RAM. The interrupt line goes low with each FIFO/Sensor
RAM read and returns high if there is still information in the RAM. In a
sensor mode, the interrupt line goes high whenever a change in a sensor is
detected.
SL0-SL3 Scan lines, which are used to scan the key switch or sensor matrix and
display digits. These lines can be either encoded (1 of 16) or decoded (1
of 4).
RL0-RL7 Return line inputs which are connected to the scan lines through the keys
or sensor switches. They have active internal pull-ups to keep them high
until a switch closure pulls one low. They also serve as 8-bit Input in
Strobed Input Mode.
SHIFT The shift input status is stored along with the key position on key closure
in the Scanned Keyboard modes.
CNTL/STB For keyboard mode this line is used as a control input and stored like
status on a key closure. The line is also the strobe line that enters the data
into the FIFO in the strobed input mode. (Rising Edge).
OUT A0-A3 These two ports are the outputs for the 16x4 display refresh registers. The
OUT B0-B3 data from these outputs is synchronized to the scan lines (SL0 – SL3) for
multiplexed digit displays. The two 4-bit ports may be blanked
independently and considered as one 8-bit port.
BD This output is used to blank the display during digit switching or by a
display blanking command.
The Intel 8279 is a general purpose Programmable Keyboard and Display I/O Interface
device designed for use with Intel Microprocessors.
The 8279 has two sections: keyboard and display. CPU is relieved from scanning the
keyboard or refreshing the display.
3) The Keyboard portion can provide a scanned interface to a 64-contact key
matrix.
The keyboard section will also interface to regular typewriter style keyboards
or random toggle or thumb switches, array of Sensors or Strobed Interface
Keyboards.
Key depressions can be 2-key lockout or N-key rollover.
Keyboard entries are debounced and strobed in an 8-char FIFO.
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Input Modes
1. Scanned Keyboard-with encoded (8 x 8 key keyboard) or decoded (4 x 8 key
keyboard) scan lines. A key depression generates a 6-bit encoding of key position.
Position and shift and control status are stored in the FIFO.
2. Scanned Sensor Matrix-with encoded (8 x 8 matrix switches) or decoded (4 x 8
matrix switches) scan lines. Key status (open or closed) stored in RAM addressable by
CPU.
3. Strobed Input-Data on return lines during control line strobe is transferred to FIFO.
Output Modes
1. 8 or 16 character-multiplexed displays that can be organized as dual 4-bit or single 8
bit
2. Right entry or left entry display formats.
Scan Counter: The scan counter has two modes. In the encoded mode, the counter
provides a binary count that must be externally decoded to provide the scan lines for the
keyboard and display. In the decoded mode, the scan counter decodes the least significant
2 bits and provides a decoded 1 of 4 scan.
In the Encoded mode, the scan lines are active high outputs.
In the Decoded mode, the scan lines are active low outputs.
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2. In the scanned Sensor Matrix modes, the contents of the return lines are directly
transferred to the corresponding row of the Sensor RAM (FIFO) each key scan time.
3. In Strobed input mode, the contents of the return lines are transferred to the FIFO on
the rising edge of the CNTL/STB line pulse.
The following commands program the 8279 operating modes. The commands are
sent on the Data Bus with CS low and A0 is high and are loaded to the 8279 on the rising
edge of WR.
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Left Entry : Left Entry mode is the simplest display format in that each display position
directly corresponds to a byte (or nibble) in the Display RAM. Address 0 in the RAM is
the left-most display character and address 15 (or address 7 In 8 character display) is the
right most display character.
Right Entry : Right entry is the method used by most electronic calculators. The first
entry is placed in the right most display character. The next entry is also placed in the
right most character after the display is shifted left one character.
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FlFO status is used in the Keyboard and Strobed Input modes to indicate the number of
characters in the FIFO and to indicate whether an error has occurred. There are two types
of errors possible: overrun and under run. Overrun occurs when the entry of another
character into a full FlFO is attempted. Under run occurs when the CPU tries to read an
empty FIFO. The FlFO status word also has a bit to indicate that the Display RAM was
unavailable because a Clear Display or Clear All command had not completed its
clearing operation. In Special Error Mode the S/E bit is showing the error flag and serves
as an indication to whether a simultaneous multiple closure error has occurred.
DU S/E O U F N N N
SAMPLE CODES :
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A 0100 :0000
MOV AL,00
OUT 31,AL
GO : IN AL,31
AND AL,07
JZ GO
IN AL,30
INT 3
The execution will come out of loop only after the key press. Depending on which
key is pressed (C0,C1,C8,C9), corresponding code will be stored in AL, which
can be checked using R command.
A 0100 :0000
MOV AL,02
OUT 31,AL
GO : IN AL,31
AND AL,07
JZ GO
IN AL,30
INT 3
A 0100 :0000
MOV AL,01
OUT 31,AL
GO : IN AL,31
AND AL,07
JZ GO
IN AL,30
INT 3
A 0100 :0000
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MOV AL,03
OUT 31,AL
GO : IN AL,31
AND AL,07
JZ GO
IN AL,30
INT 3
Use encoded 2-key lockout mode to accept a key-stature and display the same
using decoded 8*8-bit right entry rolling display.
A 0100 :0000
MOV AL,00
OUT 31,AL
GO : IN AL,31
AND AL,07
JZ GO
IN AL,30
MOV BL,AL
MOV AL,01
OUT 31,AL
MOV AL,90
OUT 31,AL
MOV AL,BL
OUT 30,AL
INT 3
CONNECTIONS : Since the K/B i/p is encoded i/p connect K0-K1 to L0-L1, and
since display is decoded connect SL3 to CSL3 (right entry !!).
Testing:
Observe the contents of registers to check which key is pressed. Verify the N-key
rollover as well as 2-key lockout options for both encoded as well as decoded modes.
Conclusion:
8279 successfully interfaced with 8086 system. The decoded and encoded modes for
using 2-key rollover as well as N-key lockout key sensing are tested.
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ASSIGNMENT No: 18
Title of Assignment: Write an ALP in 8086 to interface DAC & generate the following
waveforms on oscilloscope
• Square wave
• Sine wave
• Ramp wave
• Triangular wave
Relevant Theory:
Study Apparatus:
DYNA-86: (8086-SDK board)
DYNA-DAC study card
DYNA 86 Specifications:
Microprocessors: 8086, operating frequency: 8 MHz
64 KB ROM with monitor firmware (in two 27256—U30 and U32)
64 KB battery backed static RAM (in two 62256—U31 and U33)
Support chips: 8254, 8251, 8259, 8255, 8279, socket for 8087
Memory Map:
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8255 (#1) is reserved for printer interface. Hence for interfacing DAC, 8255 (#2) is used.
The DAC-01 Digital to Analog Converter card interfaces with the any of the Dynalog's
Microprocessor kit. It is used to implement analog and digital signal processing and real
time process control applications.
The DAC-01A is designed around DAC-0800 monolithic 8 bit high speed current output
digital to analog converter featuring 100 nsecs settling time (typical). DAC-01A has
adjustable voltage reference which permits full scale voltage. The Vref to full scale
current matching of better than ± 1 LSB gives ± LSB full scale error.
Precision Opamp based current to voltage converter has 20 mA output load driving
capacity. Analog input is polarity protected and buffered and has 10 ohms input
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impedance. Analog comparator has medium switching speeds (in milliseconds) and its
output is converted to TTL level and latched to avoid oscillating comparator status
reading which occures when two analog inputs of the comparator are nearly equal.
The PCB track design is sheilded to keep low noise level in the analog paths and this card
gives stable readings of the analog input. The DAC-01A card is also protected for reverse
supply polarity.
BLOCK DIAGRAM
PA0- PA0-
PA7 PA7 Analog O/p
D to A
DATA PA0- Converter
26 PIN LATCH PA7 DAC 0800
FRC
CRO
Port A and B of 8255 are designed as o/p ports and port C is designed as i/p port. The 8-
bit data i/p for DAC 0800 is written into the port A output register by the CPU. The data
is latched into LS373 by applying a soft ware generated positive going latching pulse
through bit PB0 of port B.
Sample Codes:
MOV AL,89
OUT 67,AL
MOV AL,01
OUT 63,AL
MOV AL,00
GO:OUT 61,AL
INC AL
JMP GO
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INT 3
MOV AL,89
OUT 67,AL
MOV AL,01
OUT 63,AL
BACK:MOV AL,00
GO:OUT 61,AL
INC AL
CMP AL,FF
JNE GO
G1:DEC AL
OUT 61,AL
CMP AL,00
JNZ G1
JMP BACK
INT 3
MOV AL,89
OUT 67,AL
MOV AL,01
OUT 63,AL
BACK:MOV AL,00
OUT 61,AL
CALL 0040
MOV AL,FF
OUT 61,AL
CALL 0040
JMP BACK
INT 3
Delay Routine:
MOV BX,000A
G1:MOV CX,0020
G2:DEC CX
JNZ GO
DEC BX
JNZ G1
RET
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MIL Manual
MOV AL,89
OUT 67,AL
MOV AL,01
OUT 63,AL
BACK:MOV AL,00
GO:OUT 61,AL
ADD AL,10
CALL 0040
CMP AL,F0
JNE GO
G1:SUB AL,10
OUT 61,AL
CALL 0040
CMP AL,10
JNE G1
JMP BACK
INT 3
Delay Routine:
MOV BX,000A
G1:MOV CX,0020
G2:DEC CX
JNZ GO
DEC BX
JNZ G1
RET
Testing:
Observe various waveforms on the C.R.O. and correlate the delays observed
on the C.R.O. screen with the delay routines evaluated for the given clock
speed.
Conclusion:
DAC study kit is successfully interfaced with 8086 system and various waveforms are
generated , which are observed on the C.R.O.
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ASSIGNMENT No: 19
Title of Assignment: Write a TSR Program to implement Real Time Clock (RTC). Read
the Real time from CMOS chip by suitable INT & display the RTC at the top right corner
on the screen. Access the video RAM directly in your routine
Relevant Theory:
Step 1) To create .EXE, .ASM program is first assembled using macro assembler to
produce .OBJ program.
Step 2) The object program is linked with the help of linker to produce .EXE program.
Step 3) A Program named EXE2BIN converts .EXE programs to .COM. EXE2BIN
specifies that convert exe to binary format (.COM). Since the operand of the command
always references an .EXE file, it is not necessary to write .EXE extension. The second
operand could be a name of .COM file. If we omit the extension EXE2BIN assumes BIN
which we want to rename as .COM in order to execute the program.
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EXEC Function
The DOS EXEC function (INT 21H Function 4BH) allows to load .COM and
.EXE programs from disk files, execute it and then regain control when the program is
finished. It also allows a program (called the parent) to load any other program (called the
child) from disk, execute it and then regain control when the child program is finished.
Step 1) Creates special data structure called a program segment prefix (PSP) in the
transient program memory (TPA).
Step 2) EXEC function loads the program, just before the PSP and performs any
relocation if required in case of .EXE only.
Step 3) It then sets up the segment registers and stack and transfers the control to the
program.
For .EXE programs the EXEC function may also do some additional processing like
passing parameters from parent to child through the environmental block. This block
holds certain information used by the system's command interpreter (usually
COMMAND.COM) and may also hold information to be used by transient programs
(.COM and .EXE).
PSP:
The PSP contains various linkages and pointers needed by the application
programs. It is a special data structure of 256 bytes. This structure is loaded by DOS
before the transient program is loaded. It occupies the base of the memory block
allocated to a transient program.
What is FCB:
FCB block is a special data structure used to access a file and contains FCB
functions which allow the programmer to create, open, close and delete files and to read
or write records of any size at any record position within such files.
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TSR:
Programs which remain running and resident in memory while other programs are
running are known as a "Terminate and Stay Resident" or "TSR" program. Example:
Doskey, background printing or popping off a calculator on a screen etc. Thus TSR is an
ordinary program which terminates not through the usual DOS terminate function, but
through the DOS "keep" function - interrupt 27H. This function reserves an area of
memory, used by the program so that no other programs will overwrite it. The terminate-
and-stay-resident function (Function 31H) is one of the MS-DOS services invoked
through Interrupt 21H.
Structure of a TSR:
TSR’s consist of two distinct parts that execute at different times. The first part is
the installation section, which executes only once, when MS-DOS loads the program.
The installation code performs any initialization tasks required by the TSR and then exits
through the terminate-and-stay-resident function.
The second part of the TSR, called the resident section, consists of code and data
left in memory after termination. The TSR’s resident code must be able to regain control
of the processor and execute after the program has terminated.
Types of TSR:
The simplest way to execute a TSR is to transfer control to it explicitly from
another program. Because the TSR in this case does not solicit processor control, it is
said to be passive. If the calling program can determine the TSR’s memory address, it can
grant control via a far jump or call. More commonly, a program activates a passive TSR
through a software interrupt. The installation section of the TSR writes the address of its
resident code to the proper position in the interrupt vector table. Any subsequent
program can then execute the TSR by calling the interrupt.
CMOS RTC:
CMOS is always present on Motherboard is of 64 bytes long. (MC146818) which stores
date and time. There are total 64 registers are present. There are also two ports which are
used 70H and 71H . 70H is write CMOS address port and 71H is data port which is used
to read or set data. In order to read seconds our code will looks like this :
MOV AL,02 ;02 transmitted to 70H to read seconds from 71H, 04 for min,06 for
hrs.
OUT 70H,AL
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When the machine is idle for specified time duration, screen saver pops up which could
be a blank screen or some data or picture displayed on screen. When the key is pressed,
original data get displayed on the screen by removing screen saver.
Algorithm:
Testing:
The RTC gets displayed on the screen and gets continuously updated.
Conclusion:
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ASSIGNMENT No: 20
Title of Assignment: Write a TSR Program to Activate a Beep Sound when any key is
pressed
Relevant Theory:
Terminate-and-Stay-Resident Programs
MS-DOS maintains a pointer to the beginning of unused memory. Programs load into
memory at this position and terminate execution by returning control to MS-DOS.
Normally, the pointer remains unchanged, allowing MS-DOS to reuse the same memory
when loading other programs.
A terminating program can, however, prevent other programs from loading on top of it.
These programs exit to MS-DOS through the terminate-and-stay-resident function, which
resets the free-memory pointer to a higher position. This leaves the program resident in a
protected block of memory, even though it is no longer running.
The terminate-and-stay-resident function (Function 31h) is one of the MS-DOS services
invoked through Interrupt 21h. The following fragment shows how a TSR program
terminates through Function 31h and remains resident in a 1000h-byte block of memory:
mov ah, 31h ; Request DOS Function 31h
mov al, err ; Set return code
mov dx, 100h ; Reserve 100h paragraphs
; (1000h bytes)
int 21h ; Terminate-and-stay-resident
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Structure of a TSR
TSRs consist of two distinct parts that execute at different times. The first part is the
installation section, which executes only once, when MS-DOS loads the program. The
installation code performs any initialization tasks required by the TSR and then exits
through the terminate-and-stay-resident function.
The second part of the TSR, called the resident section, consists of code and data left in
memory after termination. Though often identified with the TSR itself, the resident
section makes up only part of the entire program.
The TSR’s resident code must be able to regain control of the processor and execute after
the program has terminated. Methods of executing a TSR are classified as either passive
or active.
Passive TSRs
The simplest way to execute a TSR is to transfer control to it explicitly from another
program. Because the TSR in this case does not solicit processor control, it is said to be
passive. If the calling program can determine the TSR’s memory address, it can grant
control via a far jump or call. More commonly, a program activates a passive TSR
through a software interrupt. The installation section of the TSR writes the address of its
resident code to the proper position in the interrupt vector table (see “MS-DOS
Interrupts” in Chapter 7). Any subsequent program can then execute the TSR by calling
the interrupt.
Passive TSRs often replace existing software interrupts. For example, a passive TSR
might replace Interrupt 10h, the BIOS video service. By intercepting calls that read or
write to the screen, the TSR can access the video buffer directly, increasing display
speed.
Passive TSRs allow limited access since they can be invoked only from another program.
They have the advantage of executing within the context of the calling program, and thus
run no risk of interfering with another process. Such a risk does exist with active TSRs.
Active TSRs
The second method of executing a TSR involves signaling it through some hardware
event, such as a predetermined sequence of keystrokes. This type of TSR is “active”
because it must continually search for its startup signal. The advantage of active TSRs
lies in their accessibility. They can take control from any running application, execute,
and return, all on demand.
An active TSR, however, must not seize processor control blindly. It must contain
additional code that determines the proper moment at which to execute. The extra code
consists of one or more routines called “interrupt handlers,” described in the following
section.
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Algorithm:
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Testing:
Conclusion:
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