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Analytical Drain Current Model of Nanoscale Strained-Si/SiGe MOSFETs for Circuit Simulation

Analytical Drain Current Model of Nanoscale Strained-Si/SiGe MOSFETs for Circuit Simulation

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Vivek Venkataraman, Susheel Nawal andM. Jagadesh Kumar, "Analytical Drain Current Model of Nanoscale Strained-Si/SiGe MOSFETs for Circuit Simulation," Proceedings of the 20th International Conference on VLSI Design, pp.189-194, January 2007.
Vivek Venkataraman, Susheel Nawal andM. Jagadesh Kumar, "Analytical Drain Current Model of Nanoscale Strained-Si/SiGe MOSFETs for Circuit Simulation," Proceedings of the 20th International Conference on VLSI Design, pp.189-194, January 2007.

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Analytical Drain Current Model of Nanoscale Strained-Si/SiGe MOSFETs forAnalog Circuit Simulation
M. Jagadesh Kumar 
1
, Vivek Venkataraman
2
and Susheel Nawal
1
1
 Department of Electrical Engineering, Indian Institute of Technology, New Delhi 110016, India
 
2
 Department of Electrical and Computer Engineering, Cornell University, Ithaca, NY - 14850, USA
 
Abstract
 For nanoscale CMOS applications, strained-silicondevices have been receiving considerable attentionowing to their potential for achieving higher  performance and compatibility with conventional  silicon processing. In this work, an analytical model  for the output current characteristics (I-V) of nanoscale bulk strained-Si/SiGe MOSFETs, suitable for analog circuit simulation, is developed. Wedemonstrate significant current enhancement due to strain, even in short channel devices, attributed to thevelocity overshoot effect. The accuracy of the resultsobtained using our analytical model is verified using two-dimensional device simulations.
1. Introduction
Silicon-based MOSFETs have reached remarkablelevels of performance through device scaling.However, it is becoming increasingly hard to improvedevice performance through traditional scalingmethods. Strained-silicon devices have been receivingconsiderable attention owing to their potential for achieving higher performance due to improved carrier-transport properties, i.e., mobility and high-fieldvelocity [1], and compatibility with conventionalsilicon processing [2]-[4]. Tremendous improvementin static and dynamic CMOS circuit performance has been demonstrated using strained SOI as well asstrained-Si/SiGe MOSFETs [5].The aim of this paper is to develop a simple current-voltage analytical model for the output currentcharacteristics of nanoscale bulk strained-Si/SiGeMOSFETs taking into consideration (i) the effect of strain on mobility and velocity overshoot and (ii)impact ionization. The output characteristics of thestrained Si/SiGe MOSFETs are calculated for different
Fig.1
Cross-sectional view of the strained-Si/SiGe MOSFET
Ge mole fractions, gate oxide thickness and gate work function. The accuracy of the model has been verifiedusing two-dimensional simulation. It has beendemonstrated that our model predicts the drain currentaccurately under different bias conditions.
2. Strained-Si/SiGe nMOSFET and theeffects strain
The cross-section of the nanoscale bulk strained-Si/SiGe MOSFET considered in this study is shown inFig. 1. The low field mobility of carriers (
μ
eff 
) isenhanced due to strain in Si thin films grown pseudomorphically over a relaxed SiGe substrate [6].However, for short channel devices, high-field effectslike velocity saturation work against this enhancement,and hence the benefits of strained-Si for sub-100 nmCMOS are not obvious. In spite of this, enhancedcurrent drive and transconductance has beenexperimentally observed in deep submicron strained-Sidevices as well [7]. Non-local effects like velocityovershoot become prominent as MOSFET dimensionsshrink to the nanoscale regime, and this is directlyrelated with the aforementioned improvement incurrent drive observed in short-channel MOSFETs [8].
20th International Conference on VLSI Design (VLSID'07)0-7695-2762-0/07 $20.00 © 2007
 
It has been shown that an electric field step can resultin the electron velocity when it exceeds the saturationvelocity for a period shorter than the energy relaxationtime
τ
w
(which is an average time constant associatedwith the energy scattering process, or the time needed by the electron to once again reach equilibrium withthe lattice), thus causing the electron to approach ballistic transport conditions. Strain in the silicon thinfilm also leads to an increase in the energy relaxationtime (
τ
w
) of carriers, thus increasing the velocityovershoot [9]. Hence, to account for currentenhancement in short channel strained-Si devices, thevelocity overshoot effect has to be considered [10].
 A. Mobility considerations
The low-field mobility of carriers is enhanced instrained-Si channels on SiGe substrates due to reduced phonon scattering [11] and carrier redistribution in themodified energy-subband structure [12]. The mobilityenhancement factor ‘e
n
’ for electrons, for differentvalues of Ge mole fraction ‘x’ of the relaxed SiGesubstrate, is calculated based on theoretical models[11,13] ase
n
= 1 for x = 0,e
n
= 1.46 for x = 0.1,e
n
= 1.68 for x = 0.2 (1)The above values are found to agree well withexperimental data [14]. The electron mobilityenhancement is found to be sustained at high values of the transverse electric field ‘
 E 
eff 
’ as well (~70%enhancement (e
n
= 1.7) for x = 0.2, even for 
 E 
eff 
ashigh as 1.5 MV/cm) [3]. Using the Watt mobilitymodel, the effective mobility of inversion layer electrons in the channel at the gate-oxide/strained-Sifilm interface can be written as [15, 16, 17]:
( )
1111
effphsrc
μ μ μ μ 
= + +
(2)where
( )
0.166
48110
eff  phn
 E e
μ 
=
,
( )
2.176
59110
eff  srn
 E e
μ 
=
,
( )
1.071812
10127010
invcn A
 N e N 
μ 
=
.Here
μ 
 ph
is the mobility associated with phononscattering,
μ 
 sr 
is the mobility associated with surfaceroughness scattering and
μ 
c
is the mobility associatedwith coulomb/ionic impurity scattering, all in units of cm
2
/V.s. The transverse electric field
 E 
eff 
is given by[18]:
2
inveffSi
 N q E
ε 
⎛ = +
where
( )
oxinvGSth
 Nq
and .
dA
 NNx
In equation (3),
 N 
inv
is the inversion electron sheetdensity (per unit area),
 N 
is the bulk depletion chargedensity per unit area under the gate, and
 x
is theaverage depletion depth under the gate as given below:
( )
( )
4
22
dljdldldv
 xrxLxx x L
π 
+ +
, (4)2
dl 
 Lx
 
222
124
dl djd
 x L xrx L
θ 
+ +
, (5)
2
dl 
 Lx
where
1
sin2
dl 
 L x
θ 
⎛ = ⎞
, and
,
2
SiGebiSiGedl  A
 xqN 
ε 
=
 is the lateral source-body and drain-body depletionregion width. The parameters in equations (4) and (5)are defined in Fig. 1.
 B. Velocity overshoot effects
To account for velocity saturation in nanoscaledevices at high longitudinal electric fields, thefollowing two-region piecewise empirical model for velocity
v
 DD
(x)
versus longitudinal electric field
 E 
 x
(for electrons in the inversion layer) has been used [19, 20]:
( )
12
eff  DDxeffx sat 
vx E v
μ μ 
=+
for 
( )
 sat 
 Ex
(6)
( )
 DDs
vxv
=
at 
for 
( )
 sat 
 Ex
>
(7)where
 E 
 sat 
= 2v
 sat 
 / 
μ 
eff 
is the saturation electric field,
v
 sat 
 = 10
7
cm/s is the saturation velocity [15], and x is thedistance from the source along the channel.The above is a simple drift-diffusion model for carrier transport. However, for nanoscale devices, non-local effects like velocity overshoot play a significantrole. This overshoot occurs in scaled devices becauseof the large gradient in the longitudinal electric field inthe channel, and the average carrier transit time fromsource to drain being comparable to, or less than, theaverage energy relaxation time,
τ 
w
[21]. The carrier kinetic energy, or equivalently the carrier temperature,lags the local field due to this finite energy relaxationtime
τ 
w
, or relaxation length
δ 
(E 
 x
 )
. When carriers areinjected into the high-field region of a scaled MOSFETchannel, their random thermal kinetic energy is smaller than that implied by the local field. Since the carrier mobility is inversely proportional to the carrier energy,these carriers have mobilities that are high, andtherefore move with velocities higher than thoseimplied by a local velocity-field model, i.e., theyexperience, on the average, quasi-ballistic flow. The
 ⎞
(3)
20th International Conference on VLSI Design (VLSID'07)0-7695-2762-0/07 $20.00 © 2007
 
average velocity of the carriers can hence be higher than the saturation velocity. Thus, including thevelocity overshoot effect, the expression for carrier velocity along the channel is modified as [22-24]:
( ) ( )( )( )
2113
 x xsa DDDD x
 E dEvdvxvxvx
wx x
 EdxEdx
δ τ 
⎛ = + + ⎞
(8)Due to strain, the high field transport properties of carriers in the inversion layer are also modified.Although the change in the saturation velocity withstrain is expected to be small, transient transportcalculations at high lateral (longitudinal) fields show asignificant enhancement of the transient velocityovershoot with increasing energy splitting between theconduction subbands i.e. with increasing strain [9].This effect can be attributed to an increase in theenergy relaxation time with increasing strain [7]:
0.1
w
 ps
τ 
=
for x=0,
0.15
w
 s
τ 
=
for x=0.1,
0.2
w
 ps
τ 
=
for x=0.2 (9)where x is the Ge mole fraction in Si
1-x
Ge
x
substrate.From equations (6) and (8), we get
( )
21312
eff  satwx xeffx x sat 
vdE vx E  Edxv
μ τ μ 
⎛ = ++ ⎞
(10)To estimate the gradient of the longitudinal electricfield along the channel, we assume a quadraticvariation of the electrostatic potential along thechannel as
22
()122
 DSD
VaaVxxx LL
+
(11)where
a
is a constant that could be dependent ondevice parameters and technological features of theMOSFET. Comparing model with simulation, we get
a
 
0.2. Thus,
( )
222
 xD
dVxdEadxdxL
= =
(12)This approximation is quite valid in strong inversionconditions and similar expressions can also be found in[25, 26]. It helps us in finally obtaining a closed formanalytical expression for the output drain current.Substituting (12) into (10) we get,
( )
2
12
eff  DS  xeffx sat 
vxE E  Lv
μ μ 
⎛ = ++
where
23
 satw
av
τ 
=
.
3. Model for the output Current-voltagecharacteristics
To derive the current expression, we first write thecurrent at any point x along the channel as
( ) ( ) ( )
( )
( )
 DinvoxGSth
 IWQxvxWCVVVxvx
= =
(14)where W is the device width. Therefore,
( )( )
( )
 DoxGSth
 I vxWCVVVx
=
(15)Putting (13) in (15) and using
( )
 x
dVx E dx
=
we get:
( )( )
( )
( )
2
12
eff  DS  DeffoxGSth sat 
dVxdVx IWCVVVxvdxdxL
μ μ 
⎛ + = +⎝ 
 ⎞ ⎠
(16)By integrating the above equation from x= 0 to x= Land V(0) = 0 to V(L) =V
DS
, we arrive at
( )
2
121212
effox
2
 DSD DGSthDeffD sat 
WC kka IVV LL LvL
μ μ 
= + ++
 for 
,
 DSDSsa
V
(17)where
,
1
GSth DSsaGSth sat 
VV EL
=+
 is the drain voltage at which the carriers at the drain become velocity saturated [20]. When
 DS 
is greater than
 DS,sat 
, the velocity saturation or pinch-off pointmoves towards the source, away from the drain, by adistance
. The voltage difference
 DS 
- V 
 DS,sat 
appearsacross this distance
, where
is the channel lengthmodulation, given by [26]:
 ⎠ ⎞⎝ ⎛ =
 sat c sat  DS  DS c
 E 
,1
sinh
(18)where
( )
2
avdvcox
 xC
ε 
=+
,
2
SiSiGeav
ε ε ε 
+
,
avdv
 x
ε 
=
 and
 x
dv
, the vertical depletion region depth due to gate bias only, is defined as
2(
SiGethsubdv A
 xqN 
ε φ 
=
)
,
,
2
thFSisSi
φ φ φ 
= + Δ
,
 ⎠ ⎞⎝ ⎛ +Δ=Δ
Si sSiSi s g Si s
 N  N q E 
,,
ln)(
φ 
,
 ⎞
(13)
20th International Conference on VLSI Design (VLSID'07)0-7695-2762-0/07 $20.00 © 2007

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