A. Test Structure Design
Initial investigations of oxide thickness included devel-opment of a ﬁngered electrical capacitive test structure, asillustrated in Fig. 4, from which the oxide thickness betweentwo metal layers could be inferred using TCAD tools in con- junction with a large volume of electrical probe measure-ments (5-8, 11).
B. Short Flow Experiments
The statistical metrology methodology emphasizesshort process ﬂows. First, these enable fast feedback anddata to be gathered. Second, a shorter ﬂow ensures that thevariation being studied is not confounded with that gener-ated by subsequent processing steps. Indeed, substantialcare was taken in the test structure of Fig. 4 in order todeconvolve linewidth variation from dielectric thicknessvariation in the experiment. In later work, optical test maskshave been used with the advantage of even shorter processﬂows and complement the ﬁne line electrical test structures.
C. Design of Experiment Phases
As discussed in (8), three stages of experimental designhave been pursued in understanding variation. In the ﬁrststage, “screening” experiments seeks to explore a largespace of possible layout or process factors that might inﬂu-ence the parameter of interest. Second, “environmental”experiments have been pursued which study how criticalparameters depend on factors in a realistic circuit environ-ment (e.g. that of particular product families such as micro-processors, memory, or ASICs). Finally, modelingexperiments focus on very speciﬁc factors or their interac-tions, and probe multiple levels of those factors to providethe data needed for empirical models that capture key causaldependencies.
D. Variation Decomposition
Based on electrical or optical measurements taken onmany sites within the die, and many or all die on the wafer, akey issue is the assignment of variation in that measure todifferent sources. In particular, spatial characteristics of thevariation can provide substantial insight into the physicalcauses of the variation. Variation decomposition methods(captured in the “VarDAP” tool) have been developed whichsuccessively serve to extract key components from measure-ment data (16). First, wafer level trends are found, and arethemselves often of key concern for process control. Thetrend is removed from the data, and methods employed toextract the “die-level” variation (that is, the component of variation that is a clear signature of the die layout) usingeither 2D fourier techniques, or modiﬁed analysis of vari-ance approaches (6, 16). This is especially important inorder to enable further detailed analysis of the causal fea-ture- or layout-dependent effects on a clean set of data.Third, examination of wafer-die interaction is needed. Forexample, if the pattern dependencies and wafer level varia-tion are highly coupled, then process control decisions (usu-ally made based on wafer-level objectives) must also beaware of this die-level impact (20). For an example set of raw data (measurements based on the electrical test die (8)),this decomposition is pictured in Fig. 5.In the case of oxide CMP, we found that the die-levelvariation is much larger than the wafer level, and is a keycause for concern in the process. ANOVA methods wereused to identify both statistically signiﬁcant effects (caremust be taken even here, as spatial location within the diedestroys some apparent replications), as well as to estimatethe magnitude of effects. A second important aspect of thestatistical analysis was the merger of different combinationsof the original screening factors into more “natural” ormeaningful combinations. For example, the original designwas performed in terms of linewidths, line spaces, and num-ber of lines; we found, however, that structure “density” andin some cases “area” provided clearer explanations. At thispoint, further detailed models of the sources and causes of
Figure 3: Phases of statistical metrology development as appliedto oxide thickness and CMP variation.Figure 4: Electrical (capacitive) test structure used to infer thethickness of oxide between metal layers.
Oxide Thickness VariationWafer-Die-Wafer-DieInteractionRandomResidual
pitchareadensityCMPModelblanket rateplanarizationInterconnectStructureImpactNetlist/CircuitModelsLayoutTrade-offs(e.g. Dummy Fill)LayoutLevel
Screening Expts.& Variation Decomposition Factor Experiments &Empirical Models Characterization &Calibration Methods Variation Model / TCAD/ECAD Integration
Levellengthvan der Pauwsheet resistancestructurekelvin cdstructuresCapacitive test