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Pin Diagram
B
E
C
Apparatus Required
3. Capacitor 1 µF 1
4. Transistor BC 107 1
5. AFO (0 – 1) MHz 1
The fixed bias circuit is modified by attaching an external resistor to the emitter. This
resistor introduces negative feedback that stabilizes the Q-point. From Kirchhoff's voltage law,
the voltage across the base resistor is
Model Graph
Ib = VRb / Rb.
The way feedback controls the bias point is as follows. If Vbe is held constant and
temperature increases, emitter current increases. However, a larger Ie increases the emitter
voltage Ve = IeRe, which in turn reduces the voltage VRb across the base resistor. A lower base-
resistor voltage drop reduces the base current, which results in less collector current because Ic =
ß IB. Collector current and emitter current are related by Ic = α Ie with α ≈ 1, so increase in emitter
current with temperature is opposed, and operating point is kept stable.
Merits:
The circuit has the tendency to stabilize operating point against changes in temperature and β-
value.
Demerits:
• As β-value is fixed for a given transistor, this relation can be satisfied either by keeping
RE very large, or making RB very low.
• If RE is of large value, high VCC is necessary. This increases cost as well as precautions
necessary while handling.
• If RB is low, a separate low voltage supply should be used in the base circuit. Using two
supplies of different voltages is impractical.
• In addition to the above, RE causes ac feedback which reduces the voltage gain of the
amplifier.
Usage: The feedback also increases the input impedance of the amplifier when seen from the
base, which can be advantageous. Due to the above disadvantages, this type of biasing circuit is
used only with careful consideration of the trade-offs involved.
F = 1/2πhieC
Take F = 100Hz and hie = 1.6 KΩ
C1 = 1/ (2π X 1.6 KΩ X 100) = 0.9µF ≈ 1µF
Calculation
Bandwidth = fH - fL
Result
Thus a BJT Common Emitter Amplifier with fixed bias is designed and implemented and
the frequency response curve is plotted.
To design and construct BJT Common Emitter Amplifier using voltage bias (self bias)
with and without bypassed emitter resistor.
To measure the gain and to plot the frequency response and to determine the Gain
Bandwidth product (GBW).
Apparatus Required
3. Capacitor 1 µF 1
4. Transistor BC 107 1
5. AFO (0 – 1) MHz 1
Theory
A combination of fixed and self-bias can be used to improve stability and at the same
time overcome some of the disadvantages of the other two biasing methods. One of the most
widely used combination-bias systems is the voltage-divider type. The voltage divider is formed
using external resistors R1 and R2. The voltage across R2 forward biases the emitter junction. By
proper selection of resistors R1 and R2, the operating point of the transistor can be made
independent of β. In this circuit, the voltage divider holds the base voltage fixed independent of
base current provided the divider current is large compared to the base current. However, even
with a fixed base voltage, collector current varies with temperature (for example) so an emitter
resistor is added to stabilize the Q-point. However, to provide long-term or dc thermal stability,
and at the same time, allow minimal ac signal degeneration, the bypass capacitor (Cbp) is placed
across R3. If Cbp is large enough, rapid signal variations will not change its charge materially and
no degeneration of the signal will occur.
Merits
Model Graph
Design
Drop across VCE with the supply of 12V is given by 12V – 1V = 11V
Assume IC = 1 mA,
Design of R1 and R2
Assume R2 = 10 KΩ
R1 is assumed to be 61 KΩ
F = 1/2πhieC
Calculation
Procedure
To plot the Frequency Response
~ 11 ~ EC2208 - Electronic Circuits – I LAB
1) The frequency response curve is plotted on a semi-log scale.
2) The mid frequency voltage gain is divided by √2 and these points are marked in the
frequency response curve.
3) The high frequency point is called the upper 3dB point.
4) The lower frequency point is called the lower 3dB point.
5) The difference between the upper 3dB point and the lower 3dB point in the frequency
scale gives the bandwidth of the amplifier.
6) From the plotted graph the bandwidth is obtained. (i.e) Bandwidth = fH - fL
Result
Thus a BJT Common Emitter Amplifier is designed and implemented and the frequency
response curve is plotted.
Bandwidth =
Circuit diagram:
R1
8 KΩ
- +
BC 107
47 µF + -
AFO R2 RE 47 µF
5 mV a 10 KΩ 6 KΩ VO (CRO)
Aim:
1.
To design and construct BJT Common Collector Amplifier using voltage divider bias
(self-bias).
2. To measure the gain and to plot the frequency response & to determination of Gain
Bandwidth Product
Apparatus required:
1. Transistors - BC107
2. Regulated Power Supply
3. Audio Frequency Oscillator
4. Resistors - 6KΩ, 8KΩ, 10KΩ (all are ¼ W)
5. Capacitors - 47µF
6. CRO
Design:
Since voltage amplification is done in the transistor amplifier circuit, we assume equal
drops across VCE and Emitter Resistance RE. VRE = 6V. The quiescent current of 1mA is
assumed. We assume a standard supply of Vcc = 12V.
VCC R2
= 6.6 V
R1 + R2
12 X 10 X 103
= 6.6V
R1 + 10 X 103
120 X 103
= R1 + 10 X 103
6.6
Vs =
Gain
dB
A/max
3dB Line
fL fH frequency (Hz)
Result
Thus a BJT Common Collector Amplifier is designed and implemented and the frequency
response curve is plotted.
Bandwidth =
Specifications:
1. Transistor - BC107, 50V – 1A, 3W, 300 MHz
2. Regulated Power Supply (0- 30), 1A
VCC = 12 V
R1 RC
47 KΩ 4.7 KΩ
+ -
47 µF
- +
BC 107 BC 107
47 µF VO (CRO)
AFO R2 RE1 RE + CE
5 mV a 10 KΩ 4.7 KΩ 1 KΩ - 100 µF
1. To design a Darlington amplifier using BJT and to measure the gain and input resistance.
2. To plot the frequency response and to calculate the Gain Bandwidth Product (GBW).
Apparatus required:
1. Transistors - BC 107
2. Resistors - 1KΩ, 4.7KΩ, 47KΩ, 10KΩ (all are ¼ W)
3. Capacitors - 47µF, 100µF
4. CRO
5. AFO
6. RPS
7. Connecting wires & Breadboard
Design:
Such a DC the ICBO of the 1st stage is multiplied by (β+1) times and this will be input Base
current for the 2nd stage. Hence the 2nd stage IE current will be IE = (β+1)2ICO
For silicon transistor ICBO is the order of 10nA at room temperature β = 100.
Now,
IE = (101)2 X 10 nA
IE ≅ 105 nA ≅ 0.1mA
This current will get double with every 100 rise in temperature. So to reduce the effect of
ICBO the 1st stage ICBO flowing through the emitter of the 1st stage is not allowing to enter the 2nd
stage by paralleling a resistor between B & E of the 2nd stage T2. So the ICBO(β+1) will flow
through this resistance and a part of this current might flow through hie + βdcRE. This shunting
resistance will be the range of 1 to 4.7 KΩ.
Biasing Design:
Drop across Re is assumed to be 1V. The drop across VCE with a supply of 1.2 V is given
by 12 – 1 = 1V.
It is equal to VRC & VCE = 5.5V
RC = VRC = 5.5 KΩ (4.7 KΩ)
IC
Design of R1 & R2:
Drop across RE is 1V.
Drop across VBE1 & VBE2 is 0.6V.
Drop across the resistance R2 is VRE + VBE1 + VBE2
Tabular column:
~ 18 ~ EC2208 - Electronic Circuits – I LAB
Vs =
Frequency VO Gain = VO / VS Gain = 20 log (VO/VS)
(Hz) (Volts) (dB)
Gain
dB
A/max
3dB Line
fL fH frequency (Hz)
VCC R2
= 2.2V
R1 + R2
1.2 X 10 X 103
= 2.2
3
R1 + 10 X 10
R1 is rounded to be 47 KΩ
Procedure:
Result:
Bandwidth = fH - fL =
Specifications:
1. Transistor - BC107, 50V – 1A, 3W, 300 MHz
2. Regulated Power Supply (0- 30), 1A
Circuit diagram:
~ 20 ~ EC2208 - Electronic Circuits – I LAB
Pin Details
To design a common drain amplifier and to measure the gain, input resistance and output
resistance with and without Bootstrapping.
Apparatus required:
1. Transistor - BC-107
2. Regulated Power supply
3. Audio Frequency Oscillator
4. Resistors - 4.7KΩ, 2.7KΩ, 1MΩ
5. Capacitor - 1µ F
6. CRO
7. Bread board and connecting wires
Bias design:
Theory:
Here input is applied between gate and source & output between source and Drain. Here
Vs = VG + VGS. When a signal is applied to JFET gate via Cin,VG varies with the signal. As VGS
is fairly constant and Vs varies with Vi. Here output voltage follows the change in the signal
voltage applied to the gate, the circuit is also called as Source follower
Tabulation
~ 22 ~ EC2208 - Electronic Circuits – I LAB
Frequency (Hz) Vo (V) Gain = Vo / Vs Gain = 20log(Vo/Vs)dB
Model Graph
Procedure:
Result:
Thus a common drain amplifier is designed and the gain, input resistance and output
resistance are calculated using the measured parameters.
Apparatus required
1. Power Supply
2. CRO
3. Function Generator
4. Transistors - BC107 -1 no
5. Resistors - 1KΩ - 2 nos.
470Ω -1 no.
Formula
C.M.R.R = Ad/Ac
Theory
The Differential amplifier amplifies the difference between two input voltage signals.
Hence it is called differential amplifier.V1 and V2 are input voltages, Vo is proportional to
difference between two input signals.
If we apply two input voltages equal in all respects then in ideal case output should be
zero. But output voltage depends on the average common level of the inputs. Such an average
level of two input signals is called common mode signal
Higher the value of C.M.R.R, better the performance of the differential amplifier. To
improve C.M.R.R we have to increase differential mode gain and decrease common mode
gain
Formulae
Result
Thus a differential amplifier is constructed in both common mode and differential mode
and the corresponding gains are obtained and the CMRR is calculated.
CMRR =
Vcc=12V
Rc = 4.7KΩ
R1 = 61KΩ
1µF
- +
CRO
Vi= R2= 10KΩ +
10mv ` RE 100µF
1KΩ -
Pin Diagram
B
E
C
3-d view
Date:
Aim
To design and construct a Class – A power amplifier. To observe the output waveform
and to measure the maximum power output and to determine the efficiency
Apparatus required:
1. Transistor - BC107 - 1
2. Resistors - 1KΩ,4.7KΩ,61KΩ,10KΩ(all are ¼ watts)
3. Capacitors - 1µf,100µf(all are electrolytic)
4. CRO - (0-20MHz)
5. AFO - (0-1MHz)
6. Regulated Power Supply
7. Breadboard & Connecting Wires
Bias design:
Since voltage amplification is done in the transistor amplifier circuit, We as equal drops
across VCE & load resistance RE. The quiescent current of 1mA is assumed, we assume a
standard supply of 12V.
Drop across RE is assumed to be 1V,the drop across VCE with a supply of 12V is given by 12V-
1V=11V
It is equal to 11/2=5.5V
Now the voltage across the resistance RE is 5.5V
VCE = 5.5V
VC = 5.5V
IC = 1mA
RC = 5.5V/1mA = 5.5KΩ
Instead of using 5.5KΩ , We can use a standard value of 4.7KΩ.
It is assumed that RBB / (βdc+1) = RE / 10
Hence RBB / (βdc+1) is neglected when compared RE.
Hence VBB = IERE+VBE
Hence VBE is neglected when compared to IERE
Hence IE = VBB / RE.
Model graph:
~ 30 ~ EC2208 - Electronic Circuits – I LAB
gain (dB)
A
0.707 A
fL fh f (Hz)
Tabular column:
VI =
Procedure:
1. Connect the circuit as per the circuit diagram.
2. Set VS=10mV using AFO.
3. Keeping the input voltage constant, vary the frequency from few Hz to 1MHz in regular steps
& note down the correspondingly output voltage.
4. Plot the graph: gain Vs frequency.
5. Calculate bandwidth from the graph.
Result:
The class-A amplifier is designed, constructed and the output waveform is observed. The
maximum power output and the efficiency are determined.
Pin Diagram
B
E
C
3-d view
Aim:
To design and construct a Class – B (complementary symmetry) power amplifier.To
observe the output waveform with crossover Distortion and to measure the maximum power
output and to determine the efficiency.
Apparatus required:
Theory:
The figure illustrates a Class – B Power Amplifier, which employs one PNP, and one
NPN transistor and require no transformed. This type of amplifier uses complementary
symmetry. i.e., the two transistor have identical characteristics but one is PNP and the other
NPN.
Its operation can be explained by referring to the figure. When the signal voltage is
positive, T1 (the NPN transistor) conducts, while T2 (the PNP transistor) is cut off. When the
signal voltage is negative, T2 conducts while T1 is cut off. The load current is
iL = ic1 – ic2
some advantages of the circuit are that the transformer less operation saves on weight and
cost and balanced push – pull input signals are not required. The disadvantage is obtaining pause
of transistor matched closely enough to achieve low distortion.
Procedure:
Tabular column:
VI = 50 mV I = 1 mA
Π V min
Efficiency,η = 1−
4 Vcc
1 Vcc 2
Powergain =
Π 2 RL2
Result
Circuit diagram:
12
1N 4007 + +
500Ω -100 µF /25V
a
230 V 0 R Vdc
- a Vac
12
12
1N 4007 +
500Ω 100 µF CRO
230 V 0 R - 25 V
Vac
12
Procedure
Half wave rectifier
(i) Without Capacitor
1. Test your transformer: Give 230v, 50Hz source to the primary coil of the transformer and
observe the AC waveform of rated value without any distortion at the secondary of the
transformer.
2. Connect the half wave rectifier as shown in figure.
3. Measure the Vdc & Vac using DC and AC Voltmeters.
4. Calculate the Ripple factor r = Vac
Vdc
Note: The rectifier output consists of both AC & DC components. To block DC component
100µf (Electrolytic) Condenser is used.
5. Compare the theoretical ripple factor with the practical ripple factor.
VI(v)
T(m sec)
Without filter
T(m sec)
1. Connect the half wave rectifier with filter circuit as shown in fig.
2. Assume r= 10% of ripple peak-to-peak voltage for R= 500Ω. Calculate C using the
formula r = 1/2√3fRC
3. Connect CRO across load.
4. Keep the CRO switch in ground mode and observe the horizontal line and adjust it to the
X-axis.
5. Switch the CRO into DC mode and observe the waveform.
Result
Thus the Full wave rectifier is designed with and without capacitor filter and the
corresponding dc output voltages and the ripple factors are measured and verified with the
theoretical values.
Ripple Factor
Theoretical Practical
Specifications:
12V
D1 D2
230 V 1N 4007
+
D3 D4 R + 100 µF
500Ω a Vdc - 25 V
-
a
Vac
12V
D1 D2
230 V 1N 4007
D3 D4 + 100 µF CRO
R - 25 V
1. Test your transformer: Give 230v, 50Hz source to the primary coil of the transformer
and observe the AC waveform of rated value without any distortion at the secondary of
the transformer.
2. Connect the full wave rectifier as shown in figure.
3. Measure the Vdc & Vac using DC and AC Voltmeters.
4. Calculate the Ripple factor r = Vac
Vdc
Note: The rectifier output consists of both AC&DC components. To block DC component
100µf (Electrolytic) Condenser is used.
5. Compare the theoretical ripple factor with the practical ripple factor.
VI(v)
t (m sec)
VO (V)
With filter
Without filter
t (m sec)
1. To plot ripple peak-to-peak voltage Vs. Idc to choose C a ripple factor of 0.15 is assumed.
2. To get a variable load resistance a number of 500Ω, 5W of resistance are to be connected
in parallel. Hence Idc = Vdc /( N X 500). Where N is number of 500Ω resistances
connected in parallel.
3. Plot the graph Idc Vs ripple peak to peak.
4. The above steps are repeated for the various values of capacitance.
Result
Thus the Full wave rectifier is designed with and without capacitor filter and the
corresponding dc output voltages and the ripple factors are measured and verified with the
theoretical values.
Ripple Factor
Theoretical Practical
Specifications: