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Instruction Set
6-1
Instruction Set Nomenclature:
Status Register (SREG):SREG:Status registerC:Carry flag in status registerZ:Zero flag in status registerN:Negative flag in status registerV:Twos complement overflow indicatorS:N
⊕
V, For signed testsH:Half Carry flag in the status registerT:Transfer bit used by BLD and BST instructionsI:Global interrupt enable/disable flagRegisters and operands:Rd:Destination (and source) register in the register fileRr:Source register in the register fileR:Result after instruction is executedK:Constant literal or byte data (8 bit)k:Constant address data for program counterb:Bit in the register file or I/O register (3 bit)s:Bit in the status register (3 bit)X,Y,Z:Indirect address register (X=R27:R26,Y=R29:R28 and Z=R31:R30)P:I/O port addressq:Displacement for direct addressing (6 bit)I/O RegistersRAMPX, RAMPY, RAMPZ: Registers concatenated withthe X, Y and Z registers enabling indirect addressing of thewhole SRAM area on MCUs with more than 64K bytesSRAM.Stack:STACK:Stack for return address and pushed registersSP:Stack Pointer to STACKFlags:
⇔
:Flag affected by instruction
0
:Flag cleared by instruction
1
:Flag set by instruction
-
:Flag not affected by instruction
Conditional Branch Summary
* Interchange Rd and Rr in the operation before the test. i.e. CP Rd,Rr
→
CP Rr,Rd
TestBooleanMnemonicComplementaryBooleanMnemonicComment
Rd > RrZ
•
(N
⊕
V) = 0BRLT*Rd
≤
RrZ+(N
⊕
V) = 1BRGE*SignedRd
≥
Rr(N
⊕
V) = 0BRGERd < Rr(N
⊕
V) = 1BRLTSignedRd = RrZ = 1BREQRd
≠
RrZ = 0BRNESignedRd
≤
RrZ+(N
⊕
V) = 1BRGE*Rd > RrZ
•
(N
⊕
V) = 0BRLT*SignedRd < Rr(N
⊕
V) = 1BRLTRd
≥
Rr(N
⊕
V) = 0BRGESignedRd > RrC + Z = 0BRLO*Rd
≤
RrC + Z = 1BRSH*UnsignedRd
≥
RrC = 0BRSH/BRCCRd < RrC = 1BRLO/BRCSUnsignedRd = RrZ = 1BREQRd
≠
RrZ = 0BRNEUnsignedRd
≤
RrC + Z = 1BRSH*Rd > RrC + Z = 0BRLO*UnsignedRd < RrC = 1BRLO/BRCSRd
≥
RrC = 0BRSH/BRCCUnsignedCarryC = 1BRCSNo carryC = 0BRCCSimpleNegativeN = 1BRMIPositiveN = 0BRPLSimpleOverflowV = 1BRVSNo overflowV = 0BRVCSimpleZeroZ = 1BREQNot zeroZ = 0BRNESimple
 
Instruction Set
6-2
Complete Instruction Set Summary
√
) Not available in base-line microcontrollers
(continued)
MnemonicsOperandsDescriptionOperationFlags#ClockNote
ARITHMETIC AND LOGIC INSTRUCTIONS
ADDRd, RrAdd without CarryRd
←
Rd + RrZ,C,N,V,H 1ADCRd, RrAdd with Carry Rd
←
Rd + Rr + CZ,C,N,V,H 1ADIWRd, KAdd Immediate to WordRd+1:Rd
←
Rd+1:Rd + KZ,C,N,V 2SUBRd, RrSubtract without CarryRd
←
Rd - RrZ,C,N,V,H 1SUBIRd, KSubtract ImmediateRd
←
Rd - KZ,C,N,V,H 1SBCRd, RrSubtract with Carry Rd
←
Rd - Rr - CZ,C,N,V,H 1SBCIRd, KSubtract Immediate with CarryRd
←
Rd - K - CZ,C,N,V,H 1SBIWRd, KSubtract Immediate from WordRd+1:Rd
←
Rd+1:Rd - KZ,C,N,V 2ANDRd, RrLogical AND Rd
←
Rd . RrZ,N,V 1ANDIRd, KLogical AND with ImmediateRd
←
Rd
•
KZ,N,V 1ORRd, RrLogical OR Rd
←
Rd v RrZ,N,V 1ORIRd, KLogical OR with ImmediateRd
←
Rd v KZ,N,V 1EORRd, RrExclusive OR Rd
←
Rd
⊕
RrZ,N,V 1COMRdOne’s ComplementRd
←
$FF - RdZ,C,N,V 1NEGRdTwo’s ComplementRd
←
$00 - RdZ,C,N,V,H 1SBRRd,KSet Bit(s) in RegisterRd
←
Rd v KZ,N,V 1CBRRd,KClear Bit(s) in RegisterRd
←
Rd
•
($FFh - K)Z,N,V 1INCRdIncrementRd
←
Rd + 1Z,N,V 1DECRdDecrementRd
←
Rd - 1 Z,N,V 1TSTRdTest for Zero or MinusRd
←
Rd
•
Rd Z,N,V 1CLRRdClear RegisterRd
←
Rd
⊕
RdZ,N,V 1SERRdSet RegisterRd
←
$FFNone 1CPRd,RrCompareRd - RrZ,C,N,V,H, 1CPCRd,RrCompare with CarryRd - Rr - CZ,C,N,V,H 1CPIRd,KCompare with ImmediateRd - KZ,C,N,V,H 1
 
Instruction Set
6-3
Complete Instruction Set Summary
(continued)
(continued)
MnemonicsOperandsDescriptionOperationFlags#ClockNote
BRANCH INSTRUCTIONS
RJMPkRelative JumpPC
←
PC + k + 1 None 2IJMPIndirect Jump to (Z)PC
←
Z None 2JMPkJumpPC
←
k None 3RCALLkRelative Call Subroutine PC
←
PC + k + 1None 3ICALLIndirect Call to (Z)PC
←
ZNone 3CALLkCall Subroutine PC
←
kNone 4RETSubroutine ReturnPC
←
STACKNone 4RETIInterrupt ReturnPC
←
STACKI 4CPSERd,RrCompare, Skip if Equalif (Rd = Rr) PC
←
PC + 2 or 3None 1 / 2 / 3SBRCRr, bSkip if Bit in Register Cleared
if (Rr(b)=0) PC
←
PC + 2 or 3
None 1 / 2 / 3SBRSRr, bSkip if Bit in Register Set
if (Rr(b)=1) PC
←
PC + 2 or 3
None 1 / 2 / 3SBICP, bSkip if Bit in I/O Register Cleared
if(I/O(P,b)=0) PC
←
PC + 2 or 3
None 1 / 2 / 3SBISP, bSkip if Bit in I/O Register Set
If(I/O(P,b)=1) PC
←
PC + 2 or 3
None 1 / 2 / 3BRBSs, kBranch if Status Flag Set
if (SREG(s) = 1) then PC
←
PC+k + 1
None 1 / 2BRBCs, kBranch if Status Flag Cleared
if (SREG(s) = 0) then PC
←
PC+k + 1
None 1 / 2BREQ kBranch if Equal
if (Z = 1) then PC
←
PC + k + 1
None 1 / 2BRNE kBranch if Not Equal
if (Z = 0) then PC
←
PC + k + 1
None 1 / 2BRCS kBranch if Carry Set
if (C = 1) then PC
←
PC + k + 1
None 1 / 2BRCC kBranch if Carry Cleared
if (C = 0) then PC
←
PC + k + 1
None 1 / 2BRSH kBranch if Same or Higher
if (C = 0) then PC
←
PC + k + 1
None 1 / 2BRLO kBranch if Lower
if (C = 1) then PC
←
PC + k + 1
None 1 / 2BRMI kBranch if Minus
if (N = 1) then PC
←
PC + k + 1
None 1 / 2BRPL kBranch if Plus
if (N = 0) then PC
←
PC + k + 1
None 1 / 2BRGE kBranch if Greater or Equal, Signed
if (N
⊕
V= 0) then PC
←
PC+ k + 1
None 1 / 2BRLT kBranch if Less Than, Signed
if (N
⊕
V= 1) then PC
←
PC + k + 1
None 1 / 2BRHS kBranch if Half Carry Flag Set
if (H = 1) then PC
←
PC + k + 1
None 1 / 2BRHC kBranch if Half Carry Flag Cleared
if (H = 0) then PC
←
PC + k + 1
None 1 / 2BRTS kBranch if T Flag Set
if (T = 1) then PC
←
PC + k + 1
None 1 / 2BRTC kBranch if T Flag Cleared
if (T = 0) then PC
←
PC + k + 1
None 1 / 2BRVS kBranch if Overflow Flag is Set
if (V = 1) then PC
←
PC + k + 1
None 1 / 2BRVC kBranch if Overflow Flag is Cleared
if (V = 0) then PC
←
PC + k + 1
None 1 / 2BRIE kBranch if Interrupt Enabled
if ( I = 1) then PC
←
PC + k + 1
None 1 / 2BRID kBranch if Interrupt Disabled
if ( I = 0) then PC
←
PC + k + 1
None 1 / 2
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