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Digital Electronics (331102)

Digital Electronics (331102)

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Published by Sohil Vohra
j-k flip flop explained in digital electronics
j-k flip flop explained in digital electronics

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Published by: Sohil Vohra on Mar 04, 2010
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DIGITAL ELECTRONICS (331102)
56 |
Page
 
SOHIL VOHRA (LECTURER -
SHRI K.J. POLYTECHNIC COLLEGE, BHARUCH (C.E. DEPTT)
)
PRACTICAL: 14TO STUDY J - K FLIP FLOP
1.0
 
AIM :
 
To study J - K flip flop
2.0
 
PRIOR CONCEPTS :
 
Knowledge of working of AND, OR, NOT gate.
 
Knowledge of working of NAND and Ex - OR gates.
 
Difference between sequential circuit and combinational circuit.
 
Working of R
S flip flop.
3.0
 
INTRODUCTION :
 
The basic gated S R NAND Flip-flop suffers from two basic problems:
o
 
The S = 0 and R = 0 condition or S = R = 0 must always be avoided
 
o
 
If S or R changes state while the enable input is high the correct latchingaction will not occur.
 
To overcome these two problems the
JK Flip-Flop
was developed.
4.0
 
J
K FLIP FLOP :
 
The
JK Flip-Flop
is basically a Gated SR Flip-Flop with the addition of clock inputcircuitry that prevents the illegal or invalid output that can occur when bothinput S equals logic level "1" and input R equals logic level "1".
 
The symbol for a JK Flip-flop is similar to that of anSR Bistableas seen in theprevious tutorial except for the addition of a clock input.
 
DIGITAL ELECTRONICS (331102)
57 |
Page
 
SOHIL VOHRA (LECTURER -
SHRI K.J. POLYTECHNIC COLLEGE, BHARUCH (C.E. DEPTT)
)
 
The symbol for a JK Flip-flop is similar to that of anSR Bistableas seen in theprevious tutorial except for the addition of a clock input.
 
Both the S and the R inputs of the previous SR bistable have now been replacedby two inputs called the Jand K inputs, respectively.
 
The two 2-input NAND gates of the gated SR bistable have now been replaced bytwo 3-input AND gates with the third input of each gate connected to theoutputs Q and Q.
 
This cross coupling of the SR Flip-flop allows the previously invalid conditionof S = "1" and R = "1" state to be usefully used to turn it into a "Toggle action"as the two inputs are now interlocked.
 
If the circuit is "Set" the J inputis inhibited by the "0" status of the Q through thelower AND gate.
 
If the circuit is "Reset"the K input is inhibited by the"0" status of Q through theupper AND gate.
 
When both inputs J and K areequal to logic "1", the JK flip-flop changes state and the truth table for this isgiven below.
5.0
 
MASTER SLAVE J
K FLIP FLOP :
 
Although this circuit is an improvement on the clocked SR flip-flop it still suffersfrom timing problems called "race" if the output Q changes state before thetiming pulse of the clock input has time to go "OFF".
 
To avoid this the timing pulse period (T) must be kept as short as possible (highfrequency).
 
As this is sometimes is not possible with modern TTL IC's the muchimproved
Master-Slave JK Flip-flop
was developed.
 
This eliminates all the timing problems by using two SR flip-flops connectedtogether in series, one for the "Master" circuit, which triggers on the leading edgeof the clock pulse and the other, the "Slave" circuit, which triggers on the fallingedge of the clock pulse.
 
 
The
Master-Slave Flip-Flop
is basically two JK bistable flip-flops connectedtogether in a series configuration with the outputs from Q and Q from the "Slave"flip-flop being fed back to the inputs of the "Master" with the outputs of the
 
DIGITAL ELECTRONICS (331102)
58 |
Page
 
SOHIL VOHRA (LECTURER -
SHRI K.J. POLYTECHNIC COLLEGE, BHARUCH (C.E. DEPTT)
)
"Master" flip-flop being connected to the two inputs of the "Slave" flip-flop asshown below.
 
 
The input signals J and K are connected to the "Master" flip-flop which "locks" theinput while the clock (Clk) input ishigh at logic level "1".
 
As the clock input of the"Slave" flip-flop is the inverse(complement) of the "Master" clockinput, the outputs from the "Master"flip-flop are only "seen" by the"Slave" flip-flop when the clockinput goes "LOW" to logic level "0".Therefore on the "High-to-Low"transition of the clock pulse the locked outputs of the "Master" flip-flop are fedthrough to the JK inputs of the "Slave" flip-flop making this type of flip-flop edgeor pulse-triggered.
 
Then, the circuit accepts input data when the clock signal is "HIGH", and passesthe data to the output on the falling-edge of the clock signal. In other words,the
Master-Slave JK Flip-flop
is a "Synchronous" device as it only passes datawith the timing of the clock signal.
6.0
 
T FLIP FLOP :
 
The T flip-flop is a single inputversion of the JK flip-flop. Asshown inFigure ,the T flip-flop is obtained from the JKtype if both inputs are tiedtogether. The output of the Tflip-flop "toggles" with eachclock pulse.
 
The toggle, or T, flip-flop is abistable device that changes state on command from a common input terminal.
 
 
Basically, a flip flop has two inputs.One input is a control input. For a Dflip flop, the control input is labelledD. For a T flip flop, the control input islabelled T.
 
The other input is the clock. You canread about clock from the class noteson clock.

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