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I-P and O-P Capacitor Selection

I-P and O-P Capacitor Selection

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Published by: ashish19183 on Mar 14, 2010
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07/07/2010

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 Application Report 
SLTA055–FEBRUARY 2006
 Input and Output Capacitor Selection
 Jason Arrigo
..........................................................................................................
PMP Plug-In Power 
ABSTRACT
When designing with switching regulators, application requirements determine howmuch input an output capacitance is needed. There are a number of key concernswhich effect your selection. The electrical performance requirements of your designplay a big part in determining the amount of capacitance required. The transientrequirements of your system are very important. The load transient amplitude, voltagedeviation requirements, and capacitor impedance each affects capacitor selection.Other important issues to consider are minimizing PCB area and capacitor cost.When selecting input and output capacitance each design has specific requirementswhich much be addressed. System requirements set hard limits for a design.Depending on what you are trying to accomplish, the amount and type of capacitancecan vary.
Contents
1 Input Capacitor Selection
..........................................................................
22 Output Capacitor Selection
........................................................................
7
ListofFigures
1 Input Pulse Current vs Duty Cycle
...............................................................
22 Input Ripple Voltage Plots
.........................................................................
43 Multiple POL Modules Example
..................................................................
64 Capacitor Impedance Characteristics
............................................................
75 Impedance Limits
...................................................................................
86 Regulator Slew Rate Example Circuit
...........................................................
97 High Frequency Impedance Plot
................................................................
10
SLTA055–FEBRUARY 2006
Input and Output Capacitor Selection
1
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www.ti.com
1InputCapacitorSelection
1.1 Reduce Input Ripple Voltage1.2 Selecting Input Ceramic Capacitors
00.100.10.20.30.40.50.60.70.80.91.00.30.20.50.40.70.60.81.00.9
   R  e  c   t  a  n  g  u   l  a  r   P  u   l  s  e   C  u  r  r  e  n   t
D
Duty CycleTotal rmsdc Valueac rms
Input Capacitor Selection
The first objective in selecting input capacitors is to reduce the ripple voltage amplitude seen at the inputof the module. This reduces the rms ripple current to a level which can be handled by bulk capacitors.Ceramic capacitors placed right at the input of the regulator reduce ripple voltage amplitude. Onlyceramics have the extremely low ESR that is needed to reduce the ripple voltage amplitude. Thesecapacitors must be placed close to the regulator input pins to be effective. Even a few nanohenries of stray inductance in the capacitor current path raises the impedance at the switching frequency to levelsthat negate their effectiveness.Large bulk capacitors do not reduce ripple voltage. The ESR of aluminum electrolytics and most tantalumsare too high to allow for effective ripple reduction. Large input ripple voltage can cause large amounts of ripple current to flow in the bulk capacitors, causing excessive power dissipation in the ESR parasitic.To reduce the rms current in the bulk capacitors the ripple voltage amplitude must be reduced usingceramic capacitors. As a general rule of thumb, keeping the peak to peak ripple amplitude below 75 mVkeeps the rms currents in the bulk capacitors within acceptable limits.Load current, duty cycle, and switching frequency are several factors which determine the magnitude of the input ripple voltage.The input ripple voltage amplitude is directly proportional to the output load current. The maximum inputripple amplitude occurs at maximum output load. Also, the amplitude of the voltage ripple varies with theduty cycle of the converter. For a single phase buck regulator, the duty cycle is approximately the ratio of output to input dc voltage. A single phase buck regulator reaches its maximum ripple at 50% duty cycle.Figure 1shows the ac rms, dc, and total rms input current vs duty cycle for a single phase buck regulator.The solid curve shows the ac rms ripple amplitude. It reaches a maximum at 50% duty cycle. The chartshows how this magnitude falls off on either side of 50%. The straight solid line shows the average valueor dc component as a function of duty cycle. The curved dashed line shows the total rms current, both dcand ac, of the rectangular pulse as duty cycle varies.
NOTE: Multiphase regulators have multiple
humps
in the ac rms curve depending on the number of phases.
Figure1.InputPulseCurrentvsDutyCycle
Input and Output Capacitor Selection
2 SLTA055FEBRUARY 2006
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www.ti.com
1.3 Calculating Ceramic Capacitance
C
MIN
+
I
OUT
dc
(1
*
dc)
1000
SW
V
P(max)
dc
+
V
OUT
V
IN
h
;
h
+
Efficiency
(1)
C
MIN
+
10 A
0.3
(1
*
0.3)
1000333
75 mV
+
84
m
F
(2)
Input Capacitor Selection
UseEquation 1to determine the amount of ceramic capacitance required to reduce the ripple voltageamplitude to acceptable levels:where
SW
is the switching frequency in kHzI
OUT
is the steady state output load currentC
MIN(1)
is the minimum required ceramic input capacitance in
μ
F(Some of C
MIN
is supplied by the module)V
P(max)(2)
is the maximum allowed peak-peak ripple voltagedc is the duty cycle (as defined above)Notes:
(1)
The actual capacitance of a ceramic is less than the stated nominal value at a given dcvoltage. Make sure the actual value is equal to or greater than the calculated value.
(2)
75 mVpp is recommended Vpmax. This will yield approximately 22 mVrms of ripple voltage.
ExampleCeramicCalculation:
Given:
V
IN
= 12 V
V
OUT
= 3.3 V
I
OUT
= 10 A
η
= 90%
SW
= 333 kHz
dc = 0.3The minimum ceramic capacitance required to reduce the ripple voltage to 75 mVpp is calculated to be:The plots of ripple voltage inFigure 2show that the ripple amplitude has been reduced by approximately afactor of four once the calculated ceramic capacitors were added. The 75 mVpp ripple voltage amplitudegoal has been achieved.
SLTA055–FEBRUARY 2006
Input and Output Capacitor Selection
3
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