Sponsored by Mentor Graphics
ing the limits of classic board design
. In mobile telecom, intercon-nect and board dimensions areshrinking rapidly, while designs areusing fewer but more complex com-ponents with higher pin counts. Atthe same time, boards for network-ing and computer applications aregrowing, with more interconnect andground plane layers.Data rates of up to 10 Gbits/s areresetting frequency standards forICs. As IC vendors replace parallelbus architectures with serial asyn-chronous architectures (Third Gen-eration I/O or “3GIO”), challengessuch as jitter, lossy lines, and biterror rates are replacing delay, timing, crosstalk,overshoot, and other traditional high-speeddesign challenges. In other words, it’s no longerreliable or viable to follow “rules of thumb” in today’s high-speed rout-ing and verification.
The relatively new 3GIO technol-ogy uses standards for encoding anddecoding electrical signals in serialasynchronous architectures. Already,Intel Corp. has incorporated 3GIOtechnology into its PCI Express stan-dardization environment. A signifi-cant percentage of today’s PCBs arecurrently operating in a frequencyrange of 1 to 10 GHz.
From a PCB design perspective,most of today’s high-speed designtools lack the advanced modelingand verification requirements uti-lized by 3GIO technology. With theonset of serial asynchronous archi-tectures, these tools must furtheraccommodate new design conceptsfor routing highly constrained dif-ferential pairs
Understanding current and future PCB designchallenges in all areas of PCB design (from high-speed design, FPGA-on-board integration, teamdesign, and PCB fabrication, design, and inter-connect to library, constraint, and data manage-ment) is a critical aspect of a company’s invest-ment in a PCB design solution. This pulloutlooks at each of these challenges.
1. PCB design complexity is increasing at an accelerated rate with the addition of high-densityinterconnects, embedded components, gigabit data rates, and other technologies.2. Connections between ICs using the 3GIO architecture are routed using carefully matcheddifferential pairs.