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A Digital Multiplier Architecture Using Vedic Mathematics

A Digital Multiplier Architecture Using Vedic Mathematics

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Published by Swanand Raikar
A Digital Multiplier Architecture using Urdhva
Tiryakbhyam Sutra of Vedic Mathematics
Harpreet Singh Dhillon and Abhijit Mitra
Department of Electronics and Communication Engineering,
A Digital Multiplier Architecture using Urdhva
Tiryakbhyam Sutra of Vedic Mathematics
Harpreet Singh Dhillon and Abhijit Mitra
Department of Electronics and Communication Engineering,

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Published by: Swanand Raikar on Mar 28, 2010
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A Digital Multiplier Architecture using UrdhvaTiryakbhyam Sutra of Vedic Mathematics
Harpreet Singh Dhillon and Abhijit MitraDepartment of Electronics and Communication Engineering,Indian Institute of Technology, Guwahati 781 039, India.E-mail: harpreet@iitg.ernet.in; a.mitra@iitg.ernet.in
 Abstract
Vedic mathematics is the name given to the ancientIndian system of mathematics that was rediscovered in earlytwentieth century. Vedic mathematics is mainly based on sixteenprinciples or word-formulae which are termed as Sutras. Wediscuss a possible application of Vedic mathematics to digitalsignal processing in the light of application of Vedic multiplicationalgorithm to digital multipliers. A simple digital multiplier(referred henceforth as Vedic multiplier) architecture based onthe Urdhva Tiryakbhyam (Vertically and Cross wise) Sutra ispresented. This Sutra was traditionally used in ancient Indiafor the multiplication of two decimal numbers in relatively lesstime. In this paper, after a gentle introduction of this Sutra, itis applied to the binary number system to make it useful inthe digital hardware. The hardware architecture of the Vedicmultiplier is presented and is shown to be very similar to thatof the popular array multiplier. It is also equally likely thatmany such similar technical applications might come up fromthe storehouse of knowledge, Veda, if investigated properly.
 Index Terms
Vedic mathematics, Urdhva Tiryakbhyam, bi-nary multiplication, hardware design, array multiplier.
I. I
NTRODUCTION
V
EDIC mathematics [1] is the ancient Indian system of mathematics which mainly deals with Vedic mathemat-ical formulae and their application to various branches of mathematics. The word ‘Vedic’ is derived from the word‘Veda’ which means the store-house of all knowledge. Vedicmathematics was reconstructed from the ancient Indian scrip-tures (Vedas) by Sri Bharati Krsna Tirtha (1884-1960) after hiseight years of research on Vedas [1]. According to his research,Vedic mathematics is mainly based on sixteen principles orword-formulae which are termed as Sutras. The beauty of Vedic mathematics lies in the fact that it reduces otherwisecumbersome looking calculations in conventional mathematicsto a very simple ones [2]. This is so because the Vedicformulae are claimed to be based on the natural principleson which the human mind works. This is a very interestingfield and presents some effective algorithms which can beapplied to various branches of engineering such as computingand digital signal processing. This paper discusses a possibleapplication of Vedic mathematics to digital signal processingin the light of application of Vedic multiplication algorithm todigital multipliers [3].Digital multipliers are indispensable in the hardware imple-mentation of many important functions such as fast Fouriertransforms (FFTs) and multiply accumulate (MAC). This hasmade them the core components of all the digital signal pro-cessors (DSPs). Two most common multiplication algorithmsfollowed in the math coprocessor are array multiplicationalgorithm and booth multiplication algorithm [4]. The arraymultipliers take less computation time because the partialproducts are calculated independently in parallel. The delayassociated with the array multiplier is the time taken bythe signals to propagate through the gates that form themultiplication array.Booth multiplication is another important multiplicationalgorithm [5]. Large Booth arrays having large partial sum andpartial carry registers are required for high speed multiplica-tion and exponential operations. Multiplication of two
n
bitoperands using a radix-4 Booth recording multiplier requiresapproximately
n/
(2
m
)
clock cycles to generate the leastsignificant half of the final product, where
m
is the number of Booth recoder adder stages. Thus, a large propagation delayis associated with this case.This paper presents a simple digital multiplier architecture[3] based on the ancient Vedic mathematics Sutra (formula)called Urdhva Tiryakbhyam (Vertically and Cross wise) Sutrawhich was traditionally used for decimal system in ancientIndia. In [6], this Sutra is shown to be a much more efficientmultiplication algorithm as compared to the conventionalcounterparts. Another paper [7] has also shown the effective-ness of this sutra to reduce the
×
multiplier structureinto efficient
4
×
4
multiplier structures. However, they havementioned that this
4
×
4
muliplier section can be implementedusing any efficient multiplication algorithm. We apply thisSutra to binary systems to make it useful in such cases. Inparticular, we develop an efficient
4
×
4
digital multiplierthat calculates the partial products in parallel and hence thecomputation time involved is less. The architecture of thedesigned Vedic multiplier comes out to be very similar to thatof the popular array multiplier and hence it should be notedthat Vedic mathematics provides much simpler derivation of array multiplier than the conventional mathematics.This paper is organized as follows. In Section 2, a brief overview of the Vedic mathematics is provided and the Vedicmultiplication algorithm is discussed in detail. Section 3provides the hardware architecture of the proposed Vedicmultiplier. The paper is concluded in Section 4 by summer-izing the importance of the Vedic mathematics in the field of engineering.
 
3 2 57 3 8Result = 4 0Prev. Carry = 004Carry = 43 2 57 3 83 2 57 3 8STEP 3Prev. Carry = 3Result = 6 5868 5 0Carry = 63 2 57 3 83 2 57 3 80STEP 1STEP 2Result = 3 1Prev. Carry = 4Carry = 35 053Result = 2 3Prev. Carry = 629Carry = 29 8 5 0STEP 4Result = 2 1Prev. Carry = 22 3 9 8 5 023STEP 5325 X 738 = 239850
Fig. 1. Multiplication of two decimal numbers by Urdhva Tiryakbhyam Sutra.
5 4 9 8100080 03121511252280147669046382
0
21 2 7 2 2 3 7
0122210
2314
PreviousCarry5498 X 2314 = 12722372
Fig. 2. Alternative way of multiplication by Urdhva Tiryakbhyam Sutra.
II. V
EDIC
M
ULTIPLICATION
A
LGORITHM
 A. The Vedic Sutras
Vedic mathematics is based on 16 Sutras (or aphorisms)dealing with various branches of mathematics like arithmetic,algebra, geometry etc. [8]. These Sutras along with their brief meanings are enlisted below alphabetically.1) (Anurupye) Shunyamanyat – If one is in ratio, the otheris zero.2) Chalana-Kalanabyham – Differences and Similarities.3) Ekadhikina Purvena By one more than the previousone.4) Ekanyunena Purvena By one less than the previousone.5) Gunakasamuchyah – The factors of the sum is equal tothe sum of the factors.6) Gunitasamuchyah – The product of the sum is equal tothe sum of the product.
O O O OO O O OO O O OO O O OO O O OO O O OO O O OO O O OO O O OO O O OO O O OO O O OO O O OO O O OSTEP 1STEP 2STEP 3STEP 4STEP 5STEP 6STEP 7
Fig. 3. Line diagram for multiplication of two 4-bit numbers.
7) Nikhilam Navatashcaramam Dashatah – All from 9 andthe last from 10.8) Paraavartya Yojayet – Transpose and adjust.9) Puranapuranabyham By the completion or non-completion.10) Sankalana-vyavakalanabhyam – By addition and by sub-traction.11) Shesanyankena Charamena – The remainders by the lastdigit.12) Shunyam Saamyasamuccaye – When the sum is thesame that sum is zero.13) Sopaantyadvayamantyam – The ultimate and twice thepenultimate.14) Urdhva-Tiryagbyham – Vertically and crosswise.
 
15) Vyashtisamanstih – Part and Whole.16) Yaavadunam – Whatever the extent of its deficiency.These methods and ideas can be directly applied totrigonometry, plain and spherical geometry, conics, calculus(both differential and integral), and applied mathematics of various kinds. As mentioned earlier, all these Sutras werereconstructed from ancient Vedic texts early in the last centuryby Sri Bharati Krsna Tirtha. Many Sub-sutras were alsodiscovered at the same time which are not discussed here.
 B. The Proposed Vedic Multiplier 
One of the mentioned Sutras in the last subsection, Urd-hva Tiryakbhyam (Vertically and Crosswise), deals with themultiplication of numbers. This Sutra has been traditionallyused for the multiplication of two numbers in the decimalnumber system. In this paper, we apply the same idea to thebinary number system to make it compatible with the digitalhardware. Let us first illustrate this Sutra with the help of anexample in which two decimal numbers are multiplied.Line diagram for the multiplication of two numbers
(325
×
728)
is shown in Fig. 1. The digits on the two ends of theline are multiplied and the result is added with the previouscarry. When there are more lines in one step, all the resultsare added to the previous carry. The least significant digit of the number thus obtained acts as one of the result digits andthe rest act as the carry for the next step. Initially the carry istaken to be zero.An alternative method of multiplication using Urdhva-Tiryak Sutra is shown in Fig. 2. The numbers to be multipliedare written on two consecutive sides of the square as shownin the figure. The square is divided into rows and columnswhere each row/column corresponds to one of the digit of either a multiplier or a multiplicand. Thus, each digit of the multiplier has a small box common to a digit of themultiplicand. These small boxes are partitioned into two halvesby the crosswise lines. Each digit of the multiplier is thenindependently multiplied with every digit of the multiplicandand the two-digit product is written in the common box. All thedigits lying on a crosswise dotted line are added to the previouscarry. The least significant digit of the obtained number actsas the result digit and the rest as the carry for the next step.Carry for the first step (i.e., the dotted line on the extremeright side) is taken to be zero.We now extend this Vedic multiplication algorithm to bi-nary number system with the preliminary knowledge that themultiplication of two bits
a
0
and
b
0
is just an AND operationand can be implemented using simple AND gate. To illustratethis multiplication scheme in binary number system, let usconsider the multiplication of two binary numbers
a
3
a
2
a
1
a
0
and
b
3
b
2
b
1
b
0
. As the result of this multiplication would bemore than 4 bits, we express it as
...r
3
r
2
r
1
r
0
. Line diagramfor multiplication of two 4-bit numbers is shown in Fig. 3which is nothing but the mapping of the Fig. 1 in binarysystem. For the sake of simplicity, each bit is represented bya circle. Least significant bit
r
0
is obtained by multiplying theleast significant bits of the multiplicand and the multiplier. Theprocess is followed according to the steps shown in Fig. 3. Asin the last case, the digits on the both sides of the line aremultiplied and added with the carry from the previous step.This generates one of the bits of the result (
r
n
) and a carry(say
c
n
). This carry is added in the next step and hence theprocess goes on. If more than one lines are there in one step,all the results are added to the previous carry. In each step,least significant bit acts as the result bit and all the other bitsact as carry. For example, if in some intermediate step, we get110, then 0 will act as result bit and 11 as the carry (referedto as
c
n
in this text). It should be clearly noted that
c
n
maybe a multi-bit number. Thus we get the following expressions:
r
0
=
a
0
b
0
,
(1)
c
1
r
1
=
a
1
b
0
+
a
0
b
1
,
(2)
c
2
r
2
=
c
1
+
a
2
b
0
+
a
1
b
1
+
a
0
b
2
,
(3)
c
3
r
3
=
c
2
+
a
3
b
0
+
a
2
b
1
+
a
1
b
2
+
a
0
b
3
,
(4)
c
4
r
4
=
c
3
+
a
3
b
1
+
a
2
b
2
+
a
1
b
3
,
(5)
c
5
r
5
=
c
4
+
a
3
b
2
+
a
2
b
3
,
(6)
c
6
r
6
=
c
5
+
a
3
b
3
(7)with
c
6
r
6
r
5
r
4
r
3
r
2
r
1
r
0
being the final product. Partial productsare calculated in parallel and hence the delay involved is justthe time it takes for the signal to propagate through the gates.III. H
ARDWARE
A
RCHITECTURE
The main advantage of the vedic multiplication algorithm(Urdhva-Tiryak Sutra) stems from the fact that it can beeasily realized in hardware. The hardware realization of a 4-bitmultiplier using this Sutra is shown in Fig. 4. This hardwaredesign is very similar to that of the famous array multiplierwhere an array of adders is requited to arrive at the finalproduct. All the partial products are calculated in parallel andthe delay associated is mainly the time taken by the carry topropagate through the adders which form the multiplicationarray.IV. C
ONCLUSION
Ancient Indian system of mathematics, known as Vedicmathematics, can be applied to various branches of engi-neering to have a deeper insight into the working of variousformulae. The algorithms based on conventional mathematicscan be simplified and even optimized by the use of VedicSutras. We have discussed one such possible application of Vedic mathematics to digital signal processing. A simple Vedicmultiplier architecture based on the Urdhva Tiryakbhyam (Ver-tically and Cross wise) Sutra of Vedic mathematics has beenpresented. The hardware architecture of the Vedic multiplier isalso depicted and is found to be very similar to that of the socalled array multiplier. This is just one of the many possibleapplications of the Vedic Mathematics to Engineering andsome serious efforts are required to fully utilize the potentialof this interesting field for the advancement of Engineeringand Technology.Although, Vedic mathematics provides many interestingSutras, but their application to the field of engineering is notyet fully studied. Knowingly or unknowingly we always useVedic Sutras in everyday world of technology. As an example,

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