10)A 1V dc source is connected to the source of an NMOS, a 0.1 nf cap is connectedto the drain, and a 5V single pulse of duration 1 us is applied to the gate. To act asan integrator,a)W/L >>1 b)W/L<<1c)W/L=1d)Cant be said from the given dataInterview 1
round :Questions from the written test which I could not answer correctly, transfer characteristics of a CMOS inverter, implementation of an FSM given a state diagram,and a riddle :-given only a 3 l and a 5 l bottle, and nothing else, how would u measure4 l water?Interview 2nd
round :What are the issues if the duty cycle of the clock in a digital ckt is changed from50%?What are the different tests you would do to verify your verilog code?How would your friends describe you?What is the greatest risk you have taken so far in life?What are the differences between academics and industry?Paper II1 simple current mirror question.2 to generate non-overlapping clock.(see Rabaey page 339)3 question on Verilog synthesis4 always@( posedge clk)begina=0;#5 a=1;endwhat is the output waveform of a?5 question on differential amplifier gain with (w/l)
6 V=vin1 – vin2 ( vin1 and vin2 are two input voltages of 1 stage diff.amplifier).Now V is varied from -5 to +5 then draw the output voltage vs V.(Vdd=+5Vss= -5).