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SANDISK

SANDISK

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Published by rAM

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Published by: rAM on May 08, 2008
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01/05/2013

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SANDISK IIT BOMBAY PAPER, 26
th
DECEMBER, 2005Written Test 45 mins1)No. of universal logic gates reqd to implement EXOR a)4 NAND b)4 NOc)5 NANDd)5 NO2)Using (A AND Bbar), we can implementa)only AND b)only Oc)any logic functiond)none3)A –V to +V pulse voltage source is connected to a RC series ckt. Draw thewaveforms of voltage across R, voltage across C, and current in the circuit.4)Draw the capacitance vs voltage characteristics of MOSFET and MOS cap, and point their differences in the HF region5)Arrange an underdamped, critically damped, and overdamped system in order of  phase margins6)Find the voltage gain of a transconductance amplifier of transconducatnce gm,with Vi at +ve terminal, C btwn –ve term and gnd, and R between –ve term andoutput7)Considering MOS caps Cgs and Cgd,a)Cgs>Cgd in cut-off region b)Cgd>Cgs in saturation regionc)Cgd=Cgs in triode regiond)None8)Draw the waveform of “A” from the verilog codeAlways(@clk)BeginA=0;#5 A=1;end;9)Draw a NORbased latch, calculate its setup time if delay of each gate is td
 
10)A 1V dc source is connected to the source of an NMOS, a 0.1 nf cap is connectedto the drain, and a 5V single pulse of duration 1 us is applied to the gate. To act asan integrator,a)W/L >>1 b)W/L<<1c)W/L=1d)Cant be said from the given dataInterview 1
st
round :Questions from the written test which I could not answer correctly, transfer characteristics of a CMOS inverter, implementation of an FSM given a state diagram,and a riddle :-given only a 3 l and a 5 l bottle, and nothing else, how would u measure4 l water?Interview 2nd
 
round :What are the issues if the duty cycle of the clock in a digital ckt is changed from50%?What are the different tests you would do to verify your verilog code?How would your friends describe you?What is the greatest risk you have taken so far in life?What are the differences between academics and industry?Paper II1 simple current mirror question.2 to generate non-overlapping clock.(see Rabaey page 339)3 question on Verilog synthesis4 always@( posedge clk)begina=0;#5 a=1;endwhat is the output waveform of a?5 question on differential amplifier gain with (w/l)
1
=2*(w/l)
2
6 V=vin1 – vin2 ( vin1 and vin2 are two input voltages of 1 stage diff.amplifier).Now V is varied from -5 to +5 then draw the output voltage vs V.(Vdd=+5Vss= -5).

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