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Verilog FAQ TIDBITS

Verilog FAQ TIDBITS

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Published by: rAM on May 08, 2008
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01/12/2013

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Verilog FAQ
 
What is VCD and is there any free tool to view it ?
 VCD - Value Change Dump format - is an ASCII file that contains the "Changes inValues of Signals". This is a STANDARD format and is compatible between differentwaveform viewers etc. Also most of the simulators can write out VCD files - both VHDL& Verilog, though in Verilog you could do it more easily (than in VHDL - where youhave to go through your simulator's C-API) with the system tasks like $dumpvars.
VCD (Value Change Data)
Verilog simulator dumps the simulation information for waveform viewing in VCDFormat (Value Change Data).
Different types of Verilog Simulators
 
There are mainly two types of simulators available.Event DrivenCycle Based
Event-based Simulator:
This Digital Logic Simulation method sacrifices performance for rich functionality:every active signal is calculated for every device it propagates through during aclock cycle. Full Event-based simulators support 4-28 states; simulation of Behavioral HDL, RTL HDL, gate, and transistor representations; full timingcalculations for all devices; and the full HDL standard. Event-based simulatorsare like a Swiss Army knife with many different features but none are particularlyfast.Event based simulators are further categorized in 2 types.Compiled-Code Simulators:This technique takes the input definition (HDL) of the design and spends timecompiling it into a new data structure in order to enable much faster calculationsduring run-time. You sacrifice compile time to be able to run large numbers of tests faster. it is used in some high end, Event-based simulators.e.g. Synopsys Inc.'s VCS Simulator converts verilog files into C code which thenbe compiled and run, just like any other executable file. It is 10 to 50 times faster than any other interpretive simulator.seehttp://www.synopsys.com/products/simulation/vcs_ds.html
 
 
Cadence's Native Compiled Verilog generates direct machine languageinstructions from verilog files.seehttp://www.cadence.com/datasheets/affirma_nc_verilog_sim.html Interpreted Code Simulators:This method of simulation allows for rapid change of the source HDL of thedesign and restart of the simulation since there is little or no compilation involvedafter every design change. This is good for interaction but leads to poor runtimes of large tests compared to Compiled Code Techniques.e.g. Cadence Design Systems Verilog - XL.seehttp://www.cadence.com/technology/pcb/products/prev_ds/verilog-xl-family.html
 
Cycle Based Simulator:
This is a Digital Logic Simulation method that eliminates unnecessarycalculations to achieve huge performance gains in verifying Boolean logic:1.) Results are only examined at the end of every clock cycle; and2.) The digital logic is the only part of the design simulated (no timingcalculations). By limiting the calculations, Cycle based Simulators can providehuge increases in performance over conventional Event-based simulators.Cycle based simulators are more like a high speed electric carving knife incomparison because they focus on a subset of the biggest problem: logicverification.Cycle based simulators are almost invariably used along with Static Timingverifier to compensate for the lost timing information coverage.In following table differences between Event based and Cycle based simulationare summarized.Event based SimulationCycle Based SimulationEvaluates inputs looking for statechangeEvaluate entire design every clock cycleSchedule events in timeNo event schedulingCalculate time delayNo delay calculations or timing checksStore state values and time No such storage. Very fast, very efficient
 
informationmemory usage.Identify timing violationsDoes not identify timing violations
 Where two simulations are appropriateComparison between Event Based and Cycle based Simulation

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/*********** DO NOT ALTER ANYTHING BELOW THIS LINE ! ************/ var s_code=s.t();if(s_code)document.write(s_code)//-->