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Lect25 2Flip Flop 2

Lect25 2Flip Flop 2

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Published by: purwant10168 on Mar 30, 2010
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Dr. D. J. Jackson Lecture 25-1Electrical & Computer Engineering
ECE380 Digital Logic
Flip-Flops, Registers andCounters:Flip-Flops
Dr. D. J. Jackson Lecture 25-2Electrical & Computer Engineering
Flip-flops
The gated latch circuits presented are levelsensitive and can change states more thanonce during the ‘active’ period of the clocksignalCircuits (storage elements) that can changetheir state no more than once during a clockperiod are also usefulTwo types of circuits with such behavior
Master-slave flip-flipEdge-triggered flip-flop
 
Dr. D. J. Jackson Lecture 25-3Electrical & Computer Engineering
Master-slave D flip-flop
Consists of 2 gated D latches
The first,
master 
, changes its state while clock=1The second,
 slave
, changes its state whileclock=0
DQQMasterSlaveDClockQQDQQQmQs
Clk Clk 
38 transistors
Dr. D. J. Jackson Lecture 25-4Electrical & Computer Engineering
Master-slave D flip-flop
When clock=1, the master tracks the values of the Dinput signal and the slave does not change
Thus Q
m
follows any changes in D and Q
s
remains constant
When the clock signal changes to 0, the masterstage stops following the changes in the D inputsignalAt the same time, the slave stage responds to thevalue of Q
m
and changes states accordinglySince Q
m
does not change when clock=0, the slavestage undergoes at most one change of state duringa clock cycleFrom an output point of view, the circuit changes Q
s
(its output) at the
negative edge
of the clock signal
 
Dr. D. J. Jackson Lecture 25-5Electrical & Computer Engineering
Master-slave D flip-flop
DClockQmQ Qs=DclockQQ
Dr. D. J. Jackson Lecture 25-6Electrical & Computer Engineering
Edge-triggered flip-flop
A circuit, similar in functionality to the master-slaveD flip-flop, can be constructed with 6 NAND gates
DClockP4P3P1P256123QQ424 transistorsDclockQQPositive-edge-triggeredD type flip-flop

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/*********** DO NOT ALTER ANYTHING BELOW THIS LINE ! ************/ var s_code=s.t();if(s_code)document.write(s_code)//-->