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2455 South Road,Poughkeepsie,NY 12601
March 11, 2010
Mr
.Roger BowlerPresidentTurboHercules SASTour Arane,33eme etage
5,
Place de la PyramideLa Defense 992088 PARIS LA DEFENSEFRANCERe: TurboHerculesDear Mr. Bowler:We have received and considered your letter
of
November
18
,2009.The comments you
provide do not lead IBM to reconsider IBM's position as set out in my letter
of
November4,2009. Your suggestion that TurboHercules was unaware that IBM hasintellectual
property rights in this area is surprising.IBM has spent many years and many billions of
dollars developing its z-architecture and technology,and
is
widely known to have many
intellectual property rights in this area.IBM's litigation against PSI for,among other
things, patent infringement and trade secret misappropriation is a matter
of
public record,and well known in the industry.According toyour own statements,yourproduct
emulates significant portions
of
IBM's proprietary instruction set architectureand IBMhas many patents that would,therefore,be infringed. For illustration,I enclose with this
letter a non-exhaustive list
ofIBM
u.S.
patents that protect innovative elements
ofIBM's
mainframe architecture and that IBM believes will be infringed byan emulator coveringthose elements.Foryour information,the enclosed list also includes a non-exhaustive
list
of
relevant IBMu
.s
.published patent applications.Apart from concerns about
unauthorized use
of
proprietaryIBM information byone or moreTurboHercules
contributors,IBM therefore has substantial concerns about infringement
of
patented IBMtechnology.In these circumstances, Itrust you will understand that IBM cannot agree to
your request to reconsider its position.
Sincerely,Mark
S.
Anzani
VP
and
Chief Technology
Officer,
IBM
System
z
Non-ExhaustiveList
ofmM
U.S.Patents and
mM
U.S. Published PatentApplications
NO.
TITLEPATENT
US
FEATURE TYPE
OR
APPLlCA
TIONNO.
1.
7,624,237
INSTRUCTIONSETCOMPARE,SWAPANDSTOREFACILITYWITH
NO
ARCHITECTUREEXTERNALSERIALIZATION
7,617,410
.
PARALLEL
SYSPLEX
SIMULTANEOUSLY UPDATING LOGICAL
TIMEOF
ARCHITECTUREDAY (TO
D)
CLOCKS
FOR
MULTIPLE CPUSINRESPONSE
TO
DETECTING A
CAR
RY
AT APREDETERM INED BIT POSlTlONOF APHYSICAL
CLOCK
3.
7,600,053
CHANNEL
SUBSYSTEMEMULATIONOF EXTENDED INPUT/
OUTPUT
ARCHITECTUREMEASUREMENT BLOCKFACILITIES
4. 7,594,094
INSTRUCTION SET
MOVE
DATA FACILITYWITH OPTIONALARCHITECTURE SPECIFICATIONS
5.
7,587,531
CHANNEL SUBSYSTEMMULTIPLE LOGICAL INPUT/
OUTPUT
SUBSYSTEMARCHITECTUREFACILITYFACILITATING USE
OF
STORAGE ACCESSKEYSARCHITECTURE
6.
7,581,074
MEMORYTO
ACCESSSTORAGEMANAGINGINPUT/
OUTPUT
INTERRUPTIONS
IN
ARCHITECTURE
7. 7,543,095
VIRTUALIZATIONNON-DEDICATED INTERRUPTIONHARDWAREENVIRONMENTSPARSING-ENHANCEMENTFACILITYARCHITECTURE
8.
7,516,304
INSTRUCTION
SET
MULTIFUNCTION
HEXADECIMAL
INSTRUCTIONARCHITECTURE
9.
7,500,084
INSTRUCTION
SET
FORMMANAGINGINPUT/
OUTPUT
INTERRUPTIONS
IN
ARCHITECTURE
10.7,454,548
VIRTUALIZATIONNON-DEDICATEDINTERRUPTIONHARDWAREENVIRONMENTS,AND METHODS
THEREFOR
11.
7,395,448
PARALLEL
SYSPLEXDIRECTLY OBTAININGBY APPLICATIONARCHITECTURE PROGRAMS INFORMATION USABLE
IN
DETERMINING
CLOCK
ACCURACY
12. 7,380,041
VIRTUALIZATIONMANAGING
INPUT
/OUTP
UT
INTERRUPTIONSINARCHITECTURENON-DEDICATED INTERRUPTIONHARDWAREENVIRONMENTS
13. 7,373,435
CHANNEL
SUBSYSTEMEXTENDEDINPUT/
OUTPUT MEASUREMENT
ARCHITECTUREBLOCK
14.
7,356,725
INSTRUCTION
SET
METHODAND APPARATUS
FOR
ADJUSTING AARCHITECTURETIM E OFDAY
CLOCK
WITHOUTADJUSTING
THE
STEPPINGRATE
OF
AN
OSCILLATOR
15. 7,356,710
INSTRUCTION
SET
SECURITY MESSAGE AUTHENTICATIONARCHITECTURE
CONTROL
INSTRUCTIONM UL
TlPLE
LOGICALINPUT/
OUTPUT
SUBSYSTEMARCHITECTURE16.
7,290,070
CHANNEL
SUBSYSTEMFACILITY
7,284,100
INVALIDATfNG STORAGE, CLEARING
BUFFER
ARCHITECTURE
17.
INSTRUCTION
SET
ENTRIES, ANDANINSTRUCTION
THEREFOR
7,281,115
METHOD,SYSTEMAND PROGRAM PRODUCT
FOR
ARCHITECTURE
18.
MEMORY
CLEARINGSELECTED STORAGE TRANSLATIONBUFFER ENTRIES
19. 7,257,718
INSTRUCTION SET
CIPHER
MESSAGE ASSIST INSTRUCTIONSARCHITECTURE
20.7,254,698
INSTRUCTION
SET
MULTIFUNCTION HEXADECIMAL INSTRUCTIONSARCHITECTURE
2l.
METHOD, SYSTEM ANDPROGRAM
PRODUCT
FORARCHITECTURE
7,197,601
MEMORY
INVALIDATINGARANGEOF SELECTEDSTORAGE
I
TRANSLATION TABLE ENTRIES
22.
VIRTUALIZATION
METHOD
AND APPARATUS
FOR
MANAGING THE
,197,585
2
NO.
US
.
FEATURETYPETITLE
pAtENT
i.
ORAPPLICA'
TIONNO
.
ARCHITECTUREEXECUTION OF A BROADCAST INSTRUCTIONONA GUEST PROCESSOR
23.7,174,550
CHANNEL SUBSYSTEM
I
SHARING COMMUNICATIONS ADAPTERS ACROSSARCHITECTUREAPLURALITY OFINPUT/OUTPUTSUBSYSTEM
IMAGES
24.7,174,274
CHANNEL SUBSYSTEM
I
GATHERING
[f0
MEASUREMENTDATADURINGARCHITECTURE
i
AN
110
OPERATIONPROCESS
25.7,159.122
INSTRUCTION SET
I
MESSAGEDIGEST INSTRUCTIONSARCHITECTURE
26.7,146,523
PARALLEL SYSPLEXMONITORINGPROCESSING MODES OF COUPLINGARCHITECTUREFACILITY STRUCTURES
27.7,130,949
VIRTUALIZATION. MANAGINGINPUT/OUTPUTINTERRUPTIONS
IN
ARCHITECTURE
I
NON-DEDICATED INTERRUPTION HARDWAREENVIRONMENTS
28.
I
7.127,599
CHANNEL SUBSYSTEM MANAGING CONFIGURATIONS OF INPUT/OUTPUTARCHITECTURE SYSTEM IMAGESOFAN INPUT/OUTPUT
I
SUBSYSTEM,WHEREINA CONFIGURATIONIS
i
MODIFIED WITHOUTRESTARTINGTHE
I
NPUT/OUTPUTSUBSYSTEM TO EFFECT A
I
ODIFICATION
29. 7,058,837
PARALLEL SYSPLEXMETHOD ANDSYSTEMFOR PROVIDING AARCHITECTUREMESSAGE-TIME-ORDERING FACILITY
30. 7,013,305
I
PARALLEL SYSPLEXMANAGING THE STATE OF COUPLING FACILITY
I
ARCHITECTURE STRUCTURES, DETECTING
BY
ONE OR MORE
I
I
SYSTEMS COUPLED TO THE COUPLING FACILITY,
I
I
THE SUSPENDED STATE OF THEDUPLEXEDI COMMAND,DETECTING BEING INDEPENDENT OFMESSAGE EXCHANGE
31-
7,003,700
PARALLELSYSPLEXHALTING EXECUTION OF DUPLEXED COMMANDSARCHITECTURE
32. 7,000,036
CHANNEL SUBSYSTEM EXTENDED INPUT/OUTPUT MEASUREMENTARCHITECTUREFACILITIES
33. 6,996,638
CHANNEL SUBSYSTEMMETHOD, SYSTEM
AND
PROGRAM PRODUCTSARCHITECTURE FOR ENHANCING INPUT/OUTPUT PROCESSING
FOR
OPERATING SYSTEMIMAGES OFACOMPUTINGENVIRONMENT
34. 6,971,002
I
PARTITIONINGMETHOD, SYSTEM, AND PRODUCT
FOR
BOOTINGA PARTITION USING ONE OF MULTIPLE,
I
I
DIFFERENT FIRMWAREIMAGESWITHOUTREBOOTING OTHER PARTITIONS
35. 6,963,940
CHANNEL SUBSYSTEMIMEASURING UTILIZATION OF INDIVIDUALARCHITECTURE COMPONENTS OFCHANNELS
36.6,963,882
PARALLEL SYSPLEX METHOD AND APP ARATUS FOR PROCESSING AARCHITECTURELISTSTRUCTURE
37. 6,944,787
PARALLEL SYSPLEXSYSTEM-MANAGED DUPLEXING OF COUPLINGARCHITECTUREFACILITYSTRUCTURES
38. 6,862,595
PARALLEL SYSPLEXMETHODAND APPARATUS
FOR
IMPLEMENTINGARCHITECTUREA SHARED MESSAGE QUEUE USING A LIST
I
STRUCTURE
I
39. 6,859,866
PARALLEL SYSPLEX SYNCHRONIZING PROCESSING OF COMMANDSARCHITECTUREINVOKED AGAINSTDUPLEXEDCOUPLINGFACILITY STRUCTURES
40. 6,813,726
1
PARALLEL SYSPLEX RESTARTING A COUPLING FACILITY
COMMAND
I
ARCHITECTUREUSING ATOKENFROM ANOTHER COUPLINGFACILITY COMMAND
41. 6,775,789
INSTRUCTIONSETMETHOD,SYSTEMAND PROGRAM PRODUCTS
3
Activity (6)