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Table Of Contents

Introductory Remarks and Glossary
1.1 WHAT IS SO SPECIAL ABOUT DIGITAL SYSTEMS?
1.2 THE YEAR 2002 AND BEYOND?
1.3 A WORD OF WARNING
1.4 GLOSSARY OF TERMS, EXPRESSIONS, AND ABBREVIATIONS
2.5.1 Conversion of Integers
2.5.2 Conversion of Fractions
2.6 SIGNED BINARY NUMBERS
2.6.1 Signed-Magnitude Representation
2.6.2 Radix Complement Representation
2.6.3 Diminished Radix Complement Representation
2.7 EXCESS (OFFSET) REPRESENTATIONS
2.8 FLOATING-POINT NUMBER SYSTEMS
2.9 BINARY ARITHMETIC
2.9.1 Direct Addition and Subtraction of Binary Numbers
2.9.2 Two's Complement Subtraction
2.9.3 One's Complement Subtraction
2.9.4 Binary Multiplication
2.10.4 Character Codes
3.1 INTRODUCTION
3.2 BINARY STATE TERMINOLOGY AND MIXED LOGIC NOTATION
3.2.1 Binary State Terminology
Background for Digital Design
3.3 INTRODUCTION TO CMOS TERMINOLOGY AND SYMBOLOGY
3.4 LOGIC LEVEL CONVERSION: THE INVERTER
3.5 TRANSMISSION GATES AND TRI-STATE DRIVERS
3.6 AND AND OR OPERATORS AND THEIR MIXED-LOGIC CIRCUIT SYMBOLOGY 87
3.6 AND AND OR OPERATORS AND THEIR MIXED-LOGIC CIRCUIT SYMBOLOGY
3.6.1 Logic Circuit Symbology for AND and OR
3.6.2 NAND Gate Realization of Logic AND and OR
3.6.3 NOR Gate Realization of Logic AND and OR
3.6.4 NAND and NOR Gate Realization of Logic Level Conversion
3.7 LOGIC LEVEL INCOMPATIBILITY: COMPLEMENTATION
3.8 READING AND CONSTRUCTION OF MIXED-LOGIC CIRCUITS 97
3.8 READING AND CONSTRUCTION OF MIXED-LOGIC CIRCUITS
3.9 XOR AND EQV OPERATORS AND THEIR MIXED-LOGIC CIRCUIT SYMBOLOGY
3.9.1 The XOR and EQV Functions of the XOR Gate
3.9.2 The XOR and EQV Functions of the EQV Gate
3.9.3 Multiple Gate Realizations of the XOR and EQV Functions
3.9.4 The Effect of Active Low Inputs to the XOR and EQV Circuit Symbols
3.9.5 Summary of Conjugate Logic Circuit Symbols for XOR and EQV Gates
3.9.6 Controlled Logic Level Conversion
3.10 LAWS OF BOOLEAN ALGEBRA
3.10.1 NOT, AND, and OR Laws
3.10.2 The Concept of Duality
3.10.4 DeMorgan's Laws
3.11 LAWS OF XOR ALGEBRA
3.11.1 Two Useful Corollaries
3.11.2 Summary of Useful Identities
3.12 WORKED EXAMPLES
Logic Function Representation and Minimization
4.1 INTRODUCTION
4.2 SOP AND POS FORMS
4.2.1 The SOP Representation
4.2.2 The POS Representation
4.3 INTRODUCTION TO LOGIC FUNCTION GRAPHICS
4.3.1 First-Order K-maps
4.3.2 Second-Order K-maps
4.3.3 Third-Order K-maps
4.3.4 Fourth-Order K-maps
4.4 KARNAUGH MAP FUNCTION MINIMIZATION
4.4.1 Examples of Function Minimization
4.4.2 Prime Implicants
4.4.3 Incompletely Specified Functions: Don't Cares
4.5 MULTIPLE OUTPUT OPTIMIZATION
4.6 ENTERED VARIABLE K-MAP MINIMIZATION
4.6.1 Incompletely Specified Functions
4.7 FUNCTION REDUCTION OF FIVE OR MORE VARIABLES
4.8 MINIMIZATION ALGORITHMS AND APPLICATION
4.8.1 The Quine-McCluskey Algorithm
4.8.2 Cube Representation and Function Reduction
4.8.3 Qualitative Description of the Espresso Algorithm
4.9 FACTORIZATION, RESUBSTITUTION, AND DECOMPOSITION METHODS
4.9.1 Factorization
4.9.2 Resubstitution Method
4.9.3 Decomposition by Using Shannon's Expansion Theorem
4.10 DESIGN AREA VS PERFORMANCE
4.11 PERSPECTIVE ON LOGIC MINIMIZATION AND OPTIMIZATION
4.12 WORKED EV K-MAP EXAMPLES
5.1 INTRODUCTION
5.2.1 Extraction Procedure and Examples
5.4 K-MAP PLOTTING AND ENTERED VARIABLE XOR PATTERNS 205
5.4 K-MAP PLOTTING AND ENTERED VARIABLE XOR PATTERNS
5.5 THE SOP-TO-EXSOP REED-MULLER TRANSFORMATION
5.6 THE POS-TO-EQPOS REED-MULLER TRANSFORMATION
5.7 EXAMPLES OF MINIMUM FUNCTION EXTRACTION
5.8 HEURISTICS FOR CRMT MINIMIZATION
5.9 INCOMPLETELY SPECIFIED FUNCTIONS
5.10 MULTIPLE OUTPUT FUNCTIONS WITH DON'T CARES
5.12 PERSPECTIVE ON THE CRMT AND CRMT/TWO-LEVEL MINIMIZATION METHODS
6.1 INTRODUCTION AND BACKGROUND
6.1.1 The Building Blocks
6.1.2 Classification of Chips
6.1.3 Performance Characteristics and Other Practical Matters
6.1.4 Part Numbering Systems
6.1.5 Design Procedure
6.2 MULTIPLEXERS
6.2.1 Multiplexer Design
6.2.2 Combinational Logic Design with MUXs
6.3 DECODERS/DEMULTIPLEXERS
6.3.1 Decoder Design
6.3.2 Combinational Logic Design with Decoders
6.4 ENCODERS
6.5 CODE CONVERTERS
6.5.1 Procedure for Code Converter Design
6.5.2 Examples of Code Converter Design
6.6 MAGNITUDE COMPARATORS
6.7 PARITY GENERATORS AND ERROR CHECKING SYSTEMS
6.8 COMBINATIONAL SHIFTERS
6.9 STEERING LOGIC AND TRI-STATE GATE APPLICATIONS
6.10 INTRODUCTION TO VHDL DESCRIPTION OF COMBINATIONAL PRIMITIVES 279
6.10 INTRODUCTION TO VHDL DESCRIPTION OF COMBINATIONAL PRIMITIVES
Programmable Logic Devices
7.1 INTRODUCTION
7.2 READ-ONLY MEMORIES
7.2.1 PROM Applications
7.3 PROGRAMMABLE LOGIC ARRAYS
7.3.1 PLA Applications
7.4 PROGRAMMABLE ARRAY LOGIC DEVICES
7.5 MIXED-LOGIC INPUTS TO AND OUTPUTS FROM ROMs, PLAs, AND PAL DEVICES
7.6 MULTIPLE PLD SCHEMES FOR AUGMENTING INPUT AND OUTPUT CAPABILITY
7.7 INTRODUCTION TO FPGAS AND OTHER GENERAL-PURPOSE DEVICES 317
7.7 INTRODUCTION TO FPGAs AND OTHER GENERAL-PURPOSE DEVICES
7.7.1 AND-OR-lnvert and OR-AND-lnvert Building Blocks
7.7.2 Actel Field Programmable Gate Arrays
7.7.3 Xilinx FPGAs
7.7.4 Other Classes of General-Purpose PLDs
7.8 CAD HELP IN PROGRAMMING PLD DEVICES
Arithmetic Devices and Arithmetic Logic Units (ALUs)
8.1 INTRODUCTION
8.2 BINARY ADDERS
8.2.1 The Half Adder
8.2.2 The Full Adder
8.2.3 Ripple-Carry Adders
8.3 BINARY SUBTRACTORS
8.3.1 Adder/Subtractors
8.3.2 Sign-Bit Error Detection
8.4 THE CARRY LOOK-AHEAD ADDER
8.5 MULTIPLE-NUMBER ADDITION AND THE CARRY-SAVE ADDER 349
8.5 MULTIPLE-NUMBER ADDITION AND THE CARRY-SAVE ADDER
8.6 MULTIPLIERS
8.7 PARALLEL DIVIDERS
8.8 ARITHMETIC AND LOGIC UNITS
8.8.1 Dedicated ALU Design Featuring R-C and CLA Capability
8.8.2 The MUX Approach to ALU Design
8.9 DUAL-RAIL SYSTEMS AND ALUs WITH COMPLETION SIGNALS 369
8.9 DUAL-RAIL SYSTEMS AND ALUs WITH COMPLETION SIGNALS
8.9.1 Carry Look-Ahead Configuration
9.2 STATIC HAZARDS IN TWO-LEVEL COMBINATIONAL LOGIC CIRCUITS
9.3 DETECTION AND ELIMINATION HAZARDS IN MULTILEVEL XOR-TYPE FUNCTIONS
9.3.1 XOP and EOS Functions
9.4 FUNCTION HAZARDS
9.5 STUCK-AT FAULTS AND THE EFFECT OF HAZARD COVER ON FAULT TESTABILITY
Introduction to Synchronous State Machine Design and Analysis
10.1 INTRODUCTION
10.1.1 A Sequence of Logic States
10.2 MODELS FOR SEQUENTIAL MACHINES
10.3 THE FULLY DOCUMENTED STATE DIAGRAM
10.4 THE BASIC MEMORY CELLS
10.4.1 The Set-Dominant Basic Cell
10.4.2 The Reset-Dominant Basic Cell
10.4.3 Combined Form of the Excitation Table
10.4.4 Mixed-Rail Outputs of the Basic Cells
10.4.5 Mixed-Rail Output Response of the Basic Cells
10.5 INTRODUCTION TO FLIP-FLOPS
10.5.1 Triggering Mechanisms
10.5.2 Types of Flip-Flops
10.5.3 Hierarchical Flow Chart and Model for Flip-Flop Design
10.6 PROCEDURE FOR FSM (FLIP-FLOP) DESIGN AND THE MAPPING ALGORITHM
10.7 THE D FLIP-FLOPS: GENERAL
10.7.1 TheD-Latch
10.7.2 The RET D Flip-Flop
10.7.3 The Master-Slave D Flip-Flop
10.8 FLIP-FLOP CONVERSION: THE T, JK FLIP-FLOPS AND MISCELLANEOUS
10.8.1 The T Flip-Flops and Their Design from D Flip-Flops
10.8.2 The JK Flip-Flops and Their Design from D Flip-Flops
10.8.3 Design of T and D Flip-Flops from JK Flip-Flops
10.8.4 Review of Excitation Tables
10.8.5 Design of Special-Purpose Flip-Flops and Latches
10.9 LATCHES AND FLIP-FLOPS WITH SERIOUS TIMING PROBLEMS: A WARN ING
1 0.1 0 ASYNCHRONOUS PRESET AND CLEAR OVERRIDES
10.11 SETUP AND HOLD-TIME REQUIREMENTS OF FLIP-FLOPS
10.12.2 Design of a Sequence Recognizer: D-to-JK K-map Conversion
10.13 ANALYSIS OF SIMPLE STATE MACHINES
10.14 VHDL DESCRIPTION OF SIMPLE STATE MACHINES
10.14.1 The VHDL Behavorial Description of the RET D Flip-flop
10.14.2 The VHDL Behavioral Description of a Simple FSM
Synchronous FSM Design Considerations and Applications
11.1 INTRODUCTION
11.2 DETECTION AND ELIMINATION OF OUTPUT RACE GLITCHES
11.2.1 ORG Analysis Procedure Involving Two Race Paths
11.2.2 Elimination of ORGs
11.3 DETECTION AND ELIMINATION OF STATIC HAZARDS IN THE OUTPUT LOGIC
11.3.1 Externally Initiated Static Hazards in the Output Logic
11 .3.3 Perspective on Static Hazards in the Output Logic of FSMs
11.4 ASYNCHRONOUS INPUTS: RULES AND CAVEATS
11.4.1 Rules Associated with Asynchronous Inputs
11.4.2 Synchronizing the Input
11.4.3 Stretching and Synchronizing the Input
11.4.4 Metastability and the Synchronizer
11.5 CLOCK SKEW
11.6 CLOCK SOURCES AND CLOCK SIGNAL SPECIFICATIONS
11.6.1 Clock-Generating Circuitry
1 1 .6.2 Clock Signal Specifications
11.6.3 Buffering and Gating the Clock
11.7 INITIALIZATION AND RESET OF THE FSM: SANITY CIRCUITS
11.7.1 Sanity Circuits
11.8 SWITCH DEBOUNCING CIRCUITS
11.8.1 The Single-Pole/Single-Throw Switch
11.8.2 The Single-Pole/Double-Throw Switch
11.8.3 The Rotary Selector Switch
11.9 APPLICATIONS TO THE DESIGN OF MORE COMPLEX STATE MACHINES
11.9.1 Design Procedure
11.9.2 Design Example: The One- to Three-Pulse Generator
11.10 ALGORITHMIC STATE MACHINE CHARTS AND STATE TABLES
11.10.1 ASM Charts
11.10.2 State Tables and State Assignment Rules
11.11 ARRAY ALGEBRAIC APPROACH TO LOGIC DESIGN
11.12 STATE MINIMIZATION
Module and Bit-Slice Devices
12.1 INTRODUCTION
12.2 REGISTERS
12.2.1 The Storage (Holding) Register
12.2.2 The Right Shift Register with Synchronous Parallel Load
12.2.3 Universal Shift Registers with Synchronous Parallel Load
12.2.4 Universal Shift Registers with Asynchronous Parallel Load
12.2.5 Branching Action of a 4-Bit USR
12.3 SYNCHRONOUS BINARY COUNTERS
12.3.1 Simple Divide-by-N Binary Counters
12.3.2 Cascadable BCD Up-Counters
12.3.7 Branching Action of a 4-Bit Parallel Loadable Up/Down Counter
12.4 SHIFT-REGISTER COUNTERS
12.4.1 Ring Counters
12.4.2 Twisted Ring Counters
12.4.3 Linear Feedback Shift Register Counters
12.5 ASYNCHRONOUS (RIPPLE) COUNTERS
Alternative Synchronous FSM Architectures and System-Level Design
13.1 INTRODUCTION
13.1.1 Choice of Components to be Considered
13.2 ARCHITECTURES CENTERED AROUND NONREGISTERED PLDs
13.2.1 Design of the One- to Three-Pulse Generator by Using a PLA
1 3.2.2 Design of the One- to Three-Pulse Generator by Using a PAL
13.2.3 Design of the One- to Three-Pulse Generator by Using a ROM
13.2.4 Design of a More Complex FSM by Using a ROM as the PLD
13.3 STATE MACHINE DESIGNS CENTERED AROUND A SHIFT REGISTER
13.5 THE ONE-HOT DESIGN METHOD
13.5.1 Use of ASMs in One-Hot Designs
13.5.2 Application of the One-Hot Method to a Serial 2's Complementer
13.5.3 One-Hot Design of a Parallel-to-Serial Adder/Subtractor Controller
13.6 SYSTEM-LEVEL DESIGN: CONTROLLER, DATA PATH, AND FUNCTIONAL PARTITION
13.6.1 Design of a Parallel-to-Serial Adder/Subtracter Control System
13.6.2 Design of a Stepping Motor Control System
13.6.3 Perspective on System-Level Design in This Text
13.7 DEALING WITH UNUSUALLY LARGE CONTROLLER AND SYSTEM-LEVEL DESIGNS
Asynchronous State Machine Design and Analysis: Basic Concepts
14.1 INTRODUCTION
14.1.1 Features of Asynchronous FSMs
14.2 THE LUMPED PATH DELAY MODELS FOR ASYNCHRONOUS FSMS 685
14.1.2 Need for Asynchronous FSMs
14.2 THE LUMPED PATH DELAY MODELS FOR ASYNCHRONOUS FSMs
14.3 FUNCTIONAL RELATIONSHIPS AND THE STABILITY CRITERIA 687
1 4.3 FUNCTIONAL RELATIONSHIPS AND THE STABILITY CRITERIA
14.4 THE EXCITATION TABLE FOR THE LPD MODEL
14.5 STATE DIAGRAMS, K-MAPS, AND STATE TABLES FOR ASYNCHRONOUS FSMs
14.5.1 The Fully Documented State Diagram
14.5.2 Next-State and Output K-maps
14.5.3 State Tables
14.6 DESIGN OF THE BASIC CELLS BY USING THE LPD MODEL
14.6.1 The Set-Dominant Basic Cell
14.6.2 The Reset-Dominant Basic Cell
14.7 DESIGN OF THE RENDEZVOUS MODULES BY USING THE NESTED CELL MODEL
14.8 DESIGN OF THE RET D FLIP-FLOP BY USING THE LPD MODEL
1 4.9 DESIGN OF THE RET JK FLIP-FLOP BY FLIP-FLOP CONVERSION
14.10 DETECTION AND ELIMINATION OF TIMING DEFECTS IN ASYNCHRONOUS FSMs
14.10.1 Endless Cycles
14.10.2 Races and Critical Races
14.10.3 Static Hazards in the NS and Output Functions
14.10.4 Essential Hazards in Asynchronous FSMs
14.11 INITIALIZATION AND RESET OF ASYNCHRONOUS FSMs 719
14.11 INITIALIZATION AND RESET OF ASYNCHRONOUS FSMs
14.12 SINGLE-TRANSITION-TIME MACHINES AND THE ARRAY ALGEBRAIC APPROACH
14.14 ONE-HOT DESIGN OF ASYNCHRONOUS STATE MACHINES
14.15 PERSPECTIVE ON STATE CODE ASSIGNMENTS OF FUNDAMENTAL MODE FSMs
14.16 DESIGN OF FUNDAMENTAL MODE FSMs BY USING PLDs
14.17 ANALYSIS OF FUNDAMENTAL MODE STATE MACHINES
The Pulse Mode Approach to Asynchronous FSM Design
15.1 INTRODUCTION
15.2 PULSE MODE MODELS AND SYSTEM REQUIREMENTS
15.2.1 Choice of Memory Elements
15.3 OTHER CHARACTERISTICS OF PULSE MODE FSMs
15.4 DESIGN EXAMPLES
15.5 ANALYSIS OF PULSE MODE FSMs
15.6 PERSPECTIVE ON THE PULSE MODE APPROACH TO FSM DESIGN 795
15.6 PERSPECTIVE ON THE PULSE MODE APPROACH TO FSM DESIGN
PROBLEMS
16.1 INTRODUCTION
16.2 EXTERNALLY ASYNCHRONOUS/INTERNALLY CLOCKED SYSTEMS AND APPLICATIONS
16.2.1 Static Logic DFLOP Design
16.2.2 Domino Logic DFLOP Design
16.2.3 Introduction to CMOS Dynamic Domino Logic
16.2.4 EAIC System Design
16.2.5 System Simulations and Real-Time Tests
16.2.6 Variations on the Theme
16.2.7 How EAIC FSMs Differ from Conventional Synchronous FSMs
16.3 ASYNCHRONOUS PROGRAMMABLE SEQUENCERS
16.3.2 Architecture and Operation of the MAC Module
1 6.3.3 Design of the MAC Module
16.3.4 MAC Module Design of a Simple FSM
16.3.5 Cascading the MAC Module
16.3.6 Programming the MAC Module
16.3.7 Metastability and the MAC Module: The Final Issue
16.3.8 Perspective on MAC Module FSM Design
16.4 ONE-HOT PROGRAMMABLE ASYNCHRONOUS SEQUENCERS
16.4.2 Design of a Four-State Asynchronous One-Hot Sequencer
16.5 EPILOGUE TO CHAPTER 16
FURTHER READING
Other Transistor Logic Families
A.1 INTRODUCTION TO THE STANDARD NMOS LOGIC FAMILY
A.2 INTRODUCTION TO THE TTL LOGIC FAMILY
A.3 PERFORMANCE CHARACTERISTICS OF IMPORTANT 1C LOGIC FAMILIES
Computer-Aided Engineering Tools
B.1 PRODUCTIVITY TOOLS BUNDLED WITH THIS TEXT
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