Configurable System-on-Chip:

Xilinx EDK

Mr. A. B. Shinde
Lecturer,
Department of Electronics Engg.,
P.V.P.I.T., Budhgaon.

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 Field-Programmable Gate Arrays (FPGAs)

 Fine-grained reconfigurable hardware

 Gate-Array: regular structure of “logic cells”, connected
through an interconnection network
 Configuration stored in SRAM, must be loaded on startup
EPROM

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 FPGA toolflow

 Hardware design is traditionally done by

HDL
(VHDL /
modeling the system in a hardware
Verilog) description language
 An FPGA “compiler” (synthesis tool)
Synthesize generates a netlist,

Netlist

Map  which is then mapped to the FPGA

technology,
Place
 the inferred components are placed on the
Route chip,
 and the connecting signals are routed
Bitstream through the interconnection network.

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 HDL Synthesis

HDL process(clk, reset)

(VHDL / begin
Verilog)
if reset = ‚1‘ then
output <= ‚0‘;
elsif rising_edge(clk) then
Synthesize output <= a XOR b;
end if;
end process;
Netlist

Map

Register
Place
a
 D Q output
Route b

clk
clear

Bitstream reset

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 Technology Mapping
Register
HDL
(VHDL /
a
 D Q output
b
Verilog)
clk
clear
Synthesize
reset

Netlist

Map

Place

Route

Bitstream

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 Place & Route

HDL
(VHDL /
Verilog)

Synthesize

Netlist

Map

Place

Route

Bitstream

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Xilinx ISE

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 Traditional Embedded System

Power Supply
Ethernet Audio CLK
CLK
MAC Codec

GP I/O Interrupt
Controller
Timer
Address
Decode
Unit
CPU UART
L
(uP / DSP) Co- C
Memory Proc. custom
CLK Controller IF-logic

SRAM SRAM SRAM Display

SDRAM SDRAM Controller

Images by H.Walder

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 Traditional Embedded System

Power Supply
Ethernet Audio CLK
CLK
MAC FPGA Codec

GP I/O Interrupt
Controller
Timer
Address
Decode
Unit
CPU UART
L
(uP / DSP) Co- C
Memory Proc. custom
CLK Controller IF-logic

SRAM SRAM SRAM Display

SDRAM SDRAM Controller

Images by H.Walder

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Configurable System on Chip (CSoC)

Audio
Codec EPROM

Power Supply

L
C

SRAM SRAM SRAM SDRAM SDRAM

Images by H.Walder

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 Advantages

 Fewer physical components

 Shorter development cycles

 Field-programmable (updates, new features...)

 Possibly higher performance through on-chip integration

 Signals on a chip can typically be clocked higher than signals across
board traces
 Optimization between modules possible

 Partial reconfigurability
 Exchange peripherals while the rest of the system keeps running

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 Embedded CPUs
 PowerPC 405 (hard core)
 32 bit embedded PowerPC RISC architecture
 Up to 450 MHz
 2x 16 kB instruction and data caches
 Memory management unit (MMU)
 Hardware multiply and divide
 Coprocessor interface (APU)
 Embedded in Virtex-II Pro and Virtex-4
 PLB and OCM bus interfaces

 MicroBlaze (soft core)

 32 bit RISC architecture
 2-64 kB instruction and data caches
 Barrel Shifter
 Hardware multiply and divide
 OPB and LMB bus interfaces
Images by Xilinx

 Others
 NIOS (Altera), ARM, PicoBlaze (Xilinx), ...

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 CoreConnect Bus Architecture

 Flexible bus architecture for embedded Systems and SoCs

 Developed by IBM
 Used by Xilinx EDK

 Processor Local Bus (PLB)

 On-Chip Peripheral Bus (OPB)
 Device Control Register Bus
(DCR)

 Alternatives:
 AMBA (Altera)
 Wishbone (OpenCores)

 Proprietary bus architectures

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 Bus Configurations

Images by H.Walder

LMB: Local Memory Bus (for on-chip memory)

OPB: On-Chip Peripheral Bus

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 CSoC Design Flow (Hardware)

 Platform description is
HDL
Platform
(VHDL /
Description
translated/assembled into netlist,
Verilog) which in turn is either
 mapped, placed and routed onto
Netlist
Synthesize FPGA, or
Generation

Netlist
Netlist VHDL

Map

Place
XST Xilinx ISE
(VHDL Edit, Map,
(Map, Place & Route)
Place & Route)  imported into ISE and used in
Route
a larger FPGA design

Bitstream

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 CSoC Design Flow (Hardware)

Platform
Description

Netlist
Generation

Netlist VHDL

XST Xilinx ISE

(VHDL Edit, Map,
(Map, Place & Route)
Place & Route)

Bitstream

FPGAs  FPGA Tool Flow  System on Chip (SoC)  SoC Tool Flow  Demonstration 16
 CSoC Design Flow (Software)

*.a
Platform Library User sources
Description Generation
*.h *.h *.c

Netlist
Compile &
Generation
Link

Netlist
Update
Bitstream *.elf

XST or ISE
(Map, Place & Route)

Bitstream Program
with
executable
Bitstream Code

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 CSoC Design Flow (Software)

*.a
Platform Library User sources
Description Generation
*.h *.h *.c

Netlist
Compile &
Generation
Link

Netlist
Update
Bitstream *.elf

XST or ISE
(Map, Place & Route)

Bitstream Program
with
executable
Bitstream Code

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 Demonstration

 Simple System: LED Counter

 Bus Configuration: DOPB
 MicroBlaze CPU
MicroBlaze CPU Core GP I/O
 Instruction- and data memories
attached to local memory buses ILMB DLMB
 General Purpose I/O (GPIO)
attached to data-side OPB
BRAM
Image by H.Walder

 Target: Xilinx Spartan-III (XC3S200)

 200’000 gates (4’320 logic cells)
 480 CLBs (24 x 20)

 216 Kbits Block RAM

 173 User I/O pins

 12 18x18 bit multipliers

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 Demonstration

Spartan III FPGA

50 MHz clock
(back side)

7-segment display

Reset button

CLK E14
LED0
RST
F13 G13
N16

N15
LED7 R16
P16
P15
Image by H.Walder

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 Any

?’s
shindesir.pvp@gmail.com

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