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rr420203-vlsi-design

# rr420203-vlsi-design

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VLSI DESIGN
VLSI DESIGN

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05/09/2014

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Code No: RR420203
Set No. 1
IV B.Tech II Semester Regular Examinations, Apr/May 2008
VLSI DESIGN
(Electrical & Electronic Engineering)
Time: 3 hours
Max Marks: 80
All Questions carry equal marks
\u22c6 \u22c6 \u22c6 \u22c6 \u22c6
1. (a) Derive an equation forIDS of an n-channel Enhancement MOSFET operating
in Saturation region.
(b) An nMOS transistor is operating in saturation region with the following pa-
rameters.VGS = 5V ;Vtn = 1.2V ;W/L = 110;\u00b5nC ox = 110\u00b5A/V2.
Find Transconductance of the device.
[8+8]
2. With neat sketches explain how npn transistor is fabricated in Bipolar process. [16]
3. Design a stick diagram for the CMOS logic shown belowY = (A +B).C
[16]
4. Design a layout diagram for the PMOS logic shown belowY =(A +B).C
[16]
5. Calculate on resistance of the circuit shown in Figure 5 from VDD to GND. If n-
channel sheet resistance Rsn = 104
\u2126 per square and p-channel sheet resistance
Rsp= 2.5\u00d7 104\u2126 per square.
[16]
Figure 5
6. Using PLA Implement Half-adder circuit.
[16]
7. What are the di\ufb00erent report \ufb01les that are provided by the place and route tool
and discuss clearly about each report \ufb01le.
[16]
8. With neat sketches explain the oxidation process in the IC fabrication process.
[16]
\u22c6 \u22c6 \u22c6 \u22c6 \u22c6
1 of 1
Code No: RR420203
Set No. 2
IV B.Tech II Semester Regular Examinations, Apr/May 2008
VLSI DESIGN
(Electrical & Electronic Engineering)
Time: 3 hours
Max Marks: 80
All Questions carry equal marks
\u22c6 \u22c6 \u22c6 \u22c6 \u22c6
1. (a) Derive an equation forIDS of an n-channel Enhancement MOSFET operating
in linear region.
(b) A PMOS transistor is operating in saturation region with the following para-
meters.VGS =\u22125V ;Vtp =\u22121.2V ;W/L = 95;\u00b5nC ox = 95\u00b5A/V2
Find Trans conductance of the device.
[8+8]
2. With neat sketches explain how Diodes and Resistors are fabricated in nMOS
process.
[16]
3. Design a stick diagram for two input CMOS NAND and NOR gates.
[16]
4. Design a layout diagram for CMOS inverter.
[16]
5. Calculate ON resistance from VDD to GND for the given inverter circuit shown in
Figure 5, If n-channel sheet resistance is 3\u00d7 104\u2126 per square.
[16]
Figure 5
6. Clearly discus about the following FPGA Technology
(a) Anti fuse Technology.
(b) Static RAM Technology.
[8+8]
7. Explain about the following EDA tools.
(a) Design Rules veri\ufb01cation.
(b) Layout vs Schematic veri\ufb01cation.
1 of 2
Code No: RR420203
Set No. 2
(c) RC calculation from layout.
[5+6+5]
8. Mention di\ufb00erent growth technologies of the thin oxides and explain about any one
technique.
[16]
\u22c6 \u22c6 \u22c6 \u22c6 \u22c6
2 of 2