Digital Electronics

Dr. Pham Ngoc Nam

©
R.Lauwereins
Imec 2001
Acknowledgement

Digital
• The main part of the slides was adopted
design
and modified from the original slides of
Combina- Prof. Rudy Lauwereins, Vice president of
torial
circuits IMEC, Leuven, Belgium with his
permission.
Sequential
circuits

FSMD
design

VHDL

1/2
©
R.Lauwereins
Imec 2001
Your instructor

Digital
• Bộ môn kỹ thuật điện tử tin học
design
 Office: C9-401
Combina-  Email: pnnam-fet@mail.hut.edu.vn
torial
circuits • Research:
Sequential
 FPGA, PSoC, hệ nhúng
circuits
 Trí tuệ nhân tạo
FSMD • Education:
design
 K37 điện tử-ĐHBK Hà nội (1997)
VHDL  Master về trí tuệ nhân tạo 1999, Đại học K.U. Leuven, vương
quốc Bỉ
 Đề tài: Nhận dạng chữ viết tay
 Tiến sỹ kỹ thuật chuyên ngành điện tử-tin học, 9/ 2004, Đại
học K.U. Leuven-IMEC, Vương Quốc Bỉ
 Đề tài: quản lý chất lượng dịch vụ trong các ứng
dụng đa phương tiện tiên tiến
©
R.Lauwereins
Imec 2001
Course contents

Digital
• Digital design
design
• Combinatorial circuits: without status
Combina-
torial • Sequential circuits: with status
circuits
• FSMD design: hardwired processors
Sequential
circuits • Language based HW design: VHDL
FSMD
design

VHDL

1/4
©
R.Lauwereins
Imec 2001
Course contents

Digital
 Digital design
design
• Combinatorial circuits: without status
Combina-
torial • Sequential circuits: with status
circuits
• FSMD design: hardwired processors
Sequential
circuits • Language based HW design: VHDL
FSMD
design

VHDL

1/5
©
R.Lauwereins
Imec 2001
Contents of “Digital Design”

Digital
• Introduction to the course
design
• Data representation
Combina-
torial • Boolean algebra
circuits
• Logical gates
Sequential
circuits

FSMD
design

VHDL

1/6
©
R.Lauwereins
Imec 2001
Contents of “Digital Design”

Digital
• Introduction to the course
design
 Course book
Combina-  Goal
torial
circuits  Exercises and laboratory sessions
 Exam
Sequential
circuits
• Data representation
FSMD • Boolean algebra
design
• Logical gates
VHDL

1/7
©
R.Lauwereins
Imec 2001
Contents of “Digital Design”

Digital
• Introduction to the course
design
 Course book
Combina-  Goal
torial
circuits  Exercises and laboratory sessions
 Exam
Sequential
circuits
• Data representation
FSMD • Boolean algebra
design
• Logical gates
VHDL

1/8
©
R.Lauwereins
Imec 2001
Course books

Digital • Mandatory:
design
 “Principles of Digital Design”, Daniel D.
Combina-
torial
Gajski, Prentice Hall, 1997, ISBN 0-13-
circuits
301144-5
Sequential
circuits
• References:
 Douglas L. Perry, VHDL: Programming by
FSMD
design
Examples, McGraw-Hill, fourth Edition, 2002.
 “Logic and Computer Design Fundamentals”, M.
VHDL
Morris Mano & Charles R. Kime, Prentice Hall,
2nd edition, 2000, ISBN 0-13-016176-4
 TS. Nguyễn Nam Quân : “Toán logic và Kỹ thuật
số”, Nhà xuất bản khoa học và kỹ thuật, 2006

1/9
©
R.Lauwereins
Imec 2001
Contents of “Digital Design”

Digital
• Introduction to the course
design
 Course book
Combina-  Goal
torial
circuits  Exercises and laboratory sessions
 Exam
Sequential
circuits
• Data representation
FSMD • Boolean algebra
design
• Logical gates
VHDL

1/10
©
R.Lauwereins
Imec 2001
Goal of the course

Digital
• Give insight in the design of digital
design
electronic systems at the gate and
Combina- register-transfer level
torial
circuits • Teach the use of modern design tools
Sequential • Offer all building blocks needed to
construct complex digital circuits,
circuits

FSMD including processors

design
• Present the difference between functional
VHDL
requirements (operation) and non-
functional requirements (cost, speed,
power, area)
• Introduce modern implementation
platforms: PLA, PLD, FPGA

1/11
©
R.Lauwereins
Imec 2001
Contents of “Digital Design”

Digital
• Introduction to the course
design
 Course book
Combina-  Goal
torial
circuits  Exercises and laboratory sessions
 Exam
Sequential
circuits
• Data representation
FSMD • Boolean algebra
design
• Logical gates
VHDL

1/12
©
R.Lauwereins
Imec 2001
Exercises and laboratory sessions

Digital
• Bài 1: Các phần tử logic cơ bản – Bộ chọn dữ liệu
design phân kênh
Combina-
• Bài 2: Các Trigơ RS, D, JK – Bộ đếm LED 7 thanh
torial
circuits • Bài 3: Làm quen với phần mềm thí nghiệm thông
qua một ví dụ thiết kế đơn giản
Sequential
circuits • Bài 4: Thiết kế bộ so sánh hai số 3 bit: Bài thí
nghiệm này giúp sinh viên luyện tập tối thiểu hóa
FSMD
design bìa Karnaugh 6 biến và biết cách thiết kế mạch logic
tổ hợp từ các phần tử logic cơ bản
VHDL
• Bài 5: Thiết kế bộ phát hiện tổ hợp bit trong một
chuỗi bit: Giúp sinh viên biết cách xây dựng máy
trạng thái và thiết kế hệ thông số bằng máy trạng
thái
• Bài 6: Thực hiện thuật toán FIR dùng cấu trúc
FSMD
1/13
©
R.Lauwereins
Imec 2001
Contents of “Digital Design”

Digital
• Introduction to the course
design
 Course book
Combina-  Goal
torial
circuits  Exercises and laboratory sessions
 Exam
Sequential
circuits
• Data representation
FSMD • Boolean algebra
design
• Logical gates
VHDL

1/14
©
R.Lauwereins
Imec 2001
Exam

Digital
• Close book
design
• Midterm exam: 30%
Combina-
torial • Final exam: 70%
circuits
• Completing lab sessions is a must before
Sequential
circuits
taking the exam

FSMD
design

VHDL

1/15
©
R.Lauwereins
Imec 2001
Contents of “Digital Design”

Digital
• Introduction to the course
design
• Data representation
Combina-  Decimal, Binary, Octal, Hexadecimal
torial
circuits  Addition, subtraction, multiplication, division
Sequential
 Negative numbers
circuits
 Integer, fixed point, fractional, floating point,
FSMD
BCD, ASCII
design
• Boolean algebra
VHDL
• Logical gates

1/16
©
R.Lauwereins
Imec 2001
Contents of “Digital Design”

Digital
• Introduction to the course
design
• Data representation
Combina-  Decimal, Binary, Octal, Hexadecimal
torial
circuits  Addition, subtraction, multiplication, division
Sequential
 Negative numbers
circuits
 Integer, fixed point, fractional, floating point,
FSMD
BCD, ASCII
design
• Boolean algebra
VHDL
• Logical gates

1/17
©
R.Lauwereins
Imec 2001
Decimal

Digital • 1234.56710=
design
 1•1000+2•100+3•10+4•1+5•0.1+6•0.01+7•0.001
Combina-  1•103+2•102+3•101+4•100+5•10-1+6•10-2+7•10-3
torial
circuits  r = radix (r = 10), d=digit (0  d  9), m = #digits
before radix point (decimal point), n = #digits
Sequential
circuits
after decimal point
m 1

d
FSMD
design
D i r i

VHDL i n

1/18
©
R.Lauwereins
Imec 2001
Binary

Digital • 1011.0112=
design
 1•8+0•4+1•2+1•1+0•0.5+1•0.25+1•0.125
Combina-  1•23+0•22+1•21+1•20+0•2-1+1•2-2+1•2-3
torial
circuits  r = radix (r = 2), d = digit (0  d  1), m = #digits
before radix point (binary point), n = #digits
Sequential
circuits
after radix point
m 1

d
FSMD
design
B i 2 i

VHDL i n

1/19
©
R.Lauwereins
Imec 2001
Octal

Digital • 7654.328=
design
 7•512+6•64+5•8+4•1+3•0.125+2•0.015625
Combina-  7•83+6•82+5•81+4•80+3•8-1+2•8-2
torial
circuits  r = radix (r = 8), d = digit (0  d  7), m = #digits
before radix point (octal point), n = #digits after
Sequential
circuits
radix point
m 1

d
FSMD
design
O i 8 i

VHDL i n

1/20
©
R.Lauwereins
Imec 2001
Hexadecimal

Digital • FEDC.7616=
design
 15•4096+14•256+13•16+12•1+7•1/16+6•1/256
Combina-  15•163+14•162+13•161+12•160+7•16-1+6•16-2
torial
circuits  r = radix (r = 16), d = digit (0  d  F), m = #digits
before radix point (hexadecimal point), n =
Sequential
circuits
#digits after radix point
m 1

d
FSMD
design
H i  16 i

VHDL i  n

1/21
©
R.Lauwereins
Imec 2001
Contents of “Digital Design”

Digital
• Introduction to the course
design
• Data representation
Combina-  Decimal, Binary, Octal, Hexadecimal
torial
circuits  Addition, subtraction, multiplication, division
Sequential
 Negative numbers
circuits
 Integer, fixed point, fractional, floating point,
FSMD
BCD, ASCII
design
• Boolean algebra
VHDL
• Logical gates

1/22
©
R.Lauwereins
Imec 2001
Binary addition
• Decimal addition
Digital
design
carry 010
Combina-
torial x 8273
circuits

y 562
Sequential
circuits
sum 8835
FSMD
design • Binary addition
VHDL carry 0011111

x 10011011

y 1010111

sum 11110010

1/23
©
R.Lauwereins
Imec 2001
Binary subtraction

Digital
design

Combina-
x 11101
torial
circuits
y 1111
Sequential
circuits
borrow 1110
FSMD
design
result 01110
VHDL

1/24
©
R.Lauwereins
Imec 2001
Binary multiplication

Digital
design
1110
Combina-
torial 1101
circuits

1110
Sequential
circuits
0000
FSMD 1110
design

1110
VHDL

10110110

• Multiplication by repeated add & shift:

number of cycles = number of bits of
multiplier
• Can be implemented in a faster way
1/25
©
R.Lauwereins
Imec 2001
Binary division

Digital
design
10111010 1110
Combina- 1110
torial 1101
circuits 1001010

Sequential 1110
circuits
10010
FSMD 0000
design
10010
VHDL
1110
100

• Division by repeated subtract & shift:

number of cycles = number of bits of
result
1/26
• Mostly done this way
©
R.Lauwereins
Imec 2001
Contents of “Digital Design”

Digital
• Introduction to the course
design
• Data representation
Combina-  Decimal, Binary, Octal, Hexadecimal
torial
circuits  Addition, subtraction, multiplication, division
Sequential
 Negative numbers
circuits
 Integer, fixed point, fractional, floating point,
FSMD
BCD, ASCII
design
• Boolean algebra
VHDL
• Logical gates

1/27
©
R.Lauwereins
Imec 2001
Sign-Magnitude representation

Digital
• Each number consists of two parts : sign
design
and magnitude
Combina-
torial
• Decimal example: +12310 (by convention
circuits also ‘123’) and -12310
Sequential • Binary: sign represented by MSB; ‘0’ =
circuits
positive, ‘1’ = negative
FSMD
design • Binary example: 011002 = +1210 en 111002
= -1210
VHDL
• A sign-magnitude integer with n bits lies
between -(2n-1-1) and +(2n-1-1) with two
representations for 0: 000...0 en 100...0
• Generic representation of a sign-
magnitude integer: B = <s,m>
1/28
 Sign-Magnitude addition and
©
R.Lauwereins
Imec 2001

subtraction
Digital
Start Start
design subtraction addition

Combina-
torial s2=s’2
circuits

Sequential
circuits no s1=s2 yes

FSMD no yes
design m1>m2

VHDL no m1<m2 yes

mr=0 mr=m2-m1 mr=m1-m2 mr=m1+m2

sr=0 sr=s2 sr=s1 sr=s1

End
1/29
 Sign-Magnitude addition and
©
R.Lauwereins
Imec 2001

subtraction
Digital
• Multiplication and division are repeated
design
add/subtract & shift and can hence be
Combina- carried out with such an adder/subtractor
torial
circuits • Sign-magnitude representation leads to
Sequential
slow, expensive adder/subtractor due to
circuits
repeated comparison and test of sign and
FSMD magnitude
design
• This is why we represent numbers mostly
VHDL using two’s complement notation

1/30
©
R.Lauwereins
Imec 2001
Two’s complement notation

Digital
• Radix-complement of a number D with m
design
digits is D* = rm - D
Combina-
torial
• eg. The 10-complement of 12310 is
circuits 103 - 12310 = 87710
Sequential • eg. The 2-complement of 11012 is
circuits
24 - 1310 = 310 = 00112
• Call D’ the digit complement, then
FSMD
design

D*=D’+1 (proof in book); this offers us an

VHDL
easier way of determining the two’s
complement:
• eg. The 2-complement of 11012 is
00102 + 00012 = 00112

1/31
©
R.Lauwereins
Imec 2001
Two’s complement notation

Digital
• How do we negate a number D, i.o.w. how
design do we obtain -D?
Combina- • D* = rm - D  D* + D = rm = 0 when we
torial
circuits
retain only the m least significant digits 
D* = -D
Sequential
circuits • eg. D=00112  D*=11002+00012=11012
D+D*=00112+11012=100002=24=0 when we
FSMD
design retain only the m least significant bits; we
may hence use D*=11012 for the binary
VHDL
representation of -D=-310
• What is the negation of D=00002?
D*=11112+00012=100002=00002
There is only 1 notation for ‘zero’
• A 2-complement integer with n bits lies
between -(2n-1) and +(2n-1-1)
1/32
©
R.Lauwereins
Imec 2001
Two’s complement notation
Decimal 2-complement Sign-magnitude
Digital -8 1000 -
design -7 1001 1111
-6 1010 1110
Combina-
torial -5 1011 1101
circuits -4 1100 1100
-3 1101 1011
Sequential
circuits
-2 1110 1010
-1 1111 1001
FSMD 0 0000 1000 & 0000
design 1 0001 0001
2 0010 0010
VHDL
3 0011 0011
4 0100 0100
5 0101 0101
6 0110 0110
7 0111 0111

Negating a 2-complement number requires many more

bit-flips than negating a sign-magnitude number:
1/33 sign-magnitude is less power hungry than 2-complement
 Two’s complement addition and
©
R.Lauwereins
Imec 2001

subtraction
Digital
design
Start Start
subtraction addition
Combina-
torial
circuits
B2=B’2+1
Sequential
circuits

FSMD
design
Br=B1+B2

VHDL

End

• The negation needed for the subtraction is done

by taking the bit-complement of B2; the addition of
the ‘1’ is done by putting the LSB carry-in of the
next addition to 1.
1/34
 Two’s complement addition and
©
R.Lauwereins
Imec 2001

subtraction
Digital
Addition
design
0010 +2 0010 +2 1110 - 2
Combina- 0100 +4 1100 - 4 1100 - 4
torial
circuits + 00000 + 00000 + 11000
0110 +6 1110 - 2 1010 - 6
Sequential
circuits
Subtraction
FSMD
design 0010 +2 0010 +2 1110 - 2
1011 (+4)’ 0011 (- 4)’ 0011 (- 4)’
VHDL
+ 00111 + 00111 + 11111
1110 - 2 0110 +6 0010 +2
Overflow

0111 +7 1001 - 7
0110 +6 1010 - 6
+ 01100 + 10000
1101 - 3 0011 +3
1/35
©
R.Lauwereins
Imec 2001
Contents of “Digital Design”

Digital
• Introduction to the course
design
• Data representation
Combina-  Decimal, Binary, Octal, Hexadecimal
torial
circuits  Addition, subtraction, multiplication, division
Sequential
 Negative numbers
circuits
 Integer, fixed point, fractional, floating point,
FSMD
BCD, ASCII
design
• Boolean algebra
VHDL
• Logical gates

1/36
 Integer, fixed point, fractional,
©
R.Lauwereins
Imec 2001

floating point
• Integer
Digital
design  int<m>: 101011.  m=6
 int<m1>+int<m2> = int<m> and mmax(m1,m2)+1
Combina-
torial  int<m1>•int<m2> = int<m> and m=m1+m2
circuits 15

Sequential
How many bits are needed for  int  m
i 0
1  ? mm1+log216
circuits
15

FSMD How many bits are needed for  int  m

i 0
1  ? m=16•m1
design
• Fixed point
VHDL  fix<i,f>: 1101.010  i = 4, f = 3
 fix<i1,f1>+fix<i2,f2> = fix<i,f> and imax(i1,i2)+1 &
fmax(f1,f2)
 fix(i1,f1)•fix(i2,f2) = fix<i,f> and i=i1+i2 & f=f1+f2
15

How many bits are needed for:  fix  i , f

1 1 ? ii1+log216 &
i 0 f=f1
1/37
 Integer, fixed point, fractional,
©
R.Lauwereins
Imec 2001

floating point
• Fractional
Digital
design  frac<f>: 0.01101  f = 5
 frac<f1>+frac<f2> = fix<1,f> and fmax(f1,f2)
Combina-
torial  frac<f1>•frac<f2> = frac<f> and f=f1+f2
circuits 15

How many bits are needed for  frac  f

1  ? ilog216 &
Sequential
circuits
i 0 f=f1

FSMD
• Floating point
design  float<m,e>: 0.11010•2^101  m = 5, e = 3

VHDL

1/38
©
R.Lauwereins
Imec 2001
BCD

Digital
• Binary Coded Decimal number
design

Combina- Decimal BCD

torial
circuits digit
0 0000
Sequential 1 0001
circuits
2 0010
FSMD 3 0011
design 4 0100
5 0101
VHDL
6 0110
7 0111
8 1000
9 1001

1/39
 ASCII
©
R.Lauwereins
Imec 2001

• American Standard Code for Information Interchange (7-bit

code)
Digital
design
b3b2b1b0 000 001 010 011 100 101 110 111
Combina- 0000 NUL DLE SP 0 @ P ‘ p
torial 0001 SOH DC1 ! 1 A Q a q
circuits
0010 STX DC2 “ 2 B R b r
Sequential 0011 ETX DC3 # 3 C S c s
circuits 0100 EOT DC4 $ 4 D T d t
0101 ENQ NAK % 5 E U e u
FSMD
design 0110 ACK SYN & 6 F V f V
0111 BEL ETB ‘ 7 G W g w
VHDL 1000 BS CAN ( 8 H X h x
1001 HT EM ) 9 I Y i y
1010 LF SUB * : J Z j z
1011 VT ESC + ; K [ k {
1100 FF FS , < L \ l |
1101 CR GS - = M ] m }
1110 SO RS . > N ^ n ~
1111 SI US / ? O _ o DEL
1/40
©
R.Lauwereins
Imec 2001
Contents of “Digital Design”

Digital
• Introduction to the course
design
• Data representation
Combina-
torial • Boolean algebra
circuits
 Axiomatic definition of Boolean algebra
Sequential  Theorems of Boolean algebra
circuits
 Boolean functions
FSMD  Canonical form
design
 Standard form
VHDL  The 16 functions of 2 variables
• Logical gates

1/41
©
R.Lauwereins
Imec 2001
Contents of “Digital Design”

Digital
• Introduction to the course
design
• Data representation
Combina-
torial • Boolean algebra
circuits
 Axiomatic definition of Boolean algebra
Sequential  Theorems of Boolean algebra
circuits
 Boolean functions
FSMD  Canonical form
design
 Standard form
VHDL  The 16 functions of 2 variables
• Logical gates

1/42
 Axiomatic definition of Boolean
©
R.Lauwereins
Imec 2001

algebra
Digital
• A1 (Closure):
design
 B is closed w.r.t. + (OR)
Combina-  B is closed w.r.t. • (AND)
torial
circuits • A2 (Identity element)
Sequential
 B has an identity element w.r.t. +, designated
circuits by 0
FSMD
 B has an identity element w.r.t. •, designated
design by 1
VHDL • A3 (Commutativity)
 B is commutative w.r.t. +, i.o.w. x+y=y+x
 B is commutative w.r.t. •, i.o.w. x•y=y•x

1/43
 Axiomatic definition of Boolean
©
R.Lauwereins
Imec 2001

algebra
Digital
• A4 (Distributivity)
design
 • is distributive w.r.t. +, i.o.w. x•(y+z)=(x•y)+
Combina-
(x•z)
torial
circuits
 + is distributive w.r.t. •, i.o.w. x+
(y•z)=(x+y)•(x+z)
Sequential
circuits • A5 (Complement element -- NOT operator)
 xB, x’B: x+x’=1
FSMD
design  xB, x’B: x•x’=0
VHDL • A6 (Cardinality bound)
 There exist at least two different elements in B

1/44
 Axiomatic definition of Boolean
©
R.Lauwereins
Imec 2001

algebra
Digital
• Differences w.r.t. ordinary algebra
design
 In ordinary algebra + is not distributive w.r.t. •:
Combina-
5+(2•4)  (5+2) • (5+4)
torial
circuits
 In boolean algebra, an inverse operation for the
addition (OR) does not exist, neither for the
Sequential multiplication (AND); subtraction and division
circuits
hence do not exist
FSMD  In ordinary algebra it is not true that x + x’ = 1
design
and x • x’ = 0
VHDL  Boolean algebra works with a finite set of
elements, whereas ordinary algebra has an
infinite set

1/45
 Axiomatic definition of Boolean
©
R.Lauwereins
Imec 2001

algebra
Digital
• Two-valued Boolean algebra (defined by
design
Shannon)
Combina-
torial
circuits AND operator OR operator
x y xy x y x+y
Sequential
circuits
0 0 0 0 0 0
0 1 0 0 1 1
FSMD 1 0 0 1 0 1
design 1 1 1 1 1 1

VHDL
NOT operator
x x’
0 1
1 0

1/46
©
R.Lauwereins
Imec 2001
Contents of “Digital Design”

Digital
• Introduction to the course
design
• Data representation
Combina-
torial • Boolean algebra
circuits
 Axiomatic definition of Boolean algebra
Sequential  Theorems of Boolean algebra
circuits
 Boolean functions
FSMD  Canonical form
design
 Standard form
VHDL  The 16 functions of 2 variables
• Logical gates

1/47
©
R.Lauwereins
Imec 2001
Theorems of Boolean algebra

Digital
• Theorem 1: idempotency
design
x + x = x
Combina-  x • x = x (Note the duality!!)
torial
circuits • Theorem 2
Sequential
x + 1 = 1
circuits
 Dual: x • 0 = 0
FSMD • Theorem 3: absorption
design
 y • x + x = x (priority: • before +)
VHDL  Dual: (y + x) • x = x
• Theorem 4: involution
 (x’)’ = x

1/48
©
R.Lauwereins
Imec 2001
Theorems of Boolean algebra

Digital
• Theorem 5: associativity
design
 (x + y) + z = x + (y + z)
Combina-  Dual: (xy)z = x(yz)
torial
circuits • Theorem 6: De Morgan’s law
Sequential
 (x+y)’ = x’y’
circuits
 Dual: (xy)’ = x’+y’
FSMD • Proof: using axioms or truth table
design
• Duality:
VHDL
 Replace each OR by AND and AND by OR
 Replace each 0 by 1 and x by x’

1/49
©
R.Lauwereins
Imec 2001
Contents of “Digital Design”

Digital
• Introduction to the course
design
• Data representation
Combina-
torial • Boolean algebra
circuits
 Axiomatic definition of Boolean algebra
Sequential  Theorems of Boolean algebra
circuits
 Boolean functions
FSMD  Canonical form
design
 Standard form
VHDL  The 16 functions of 2 variables
• Logical gates

1/50
©
R.Lauwereins
Imec 2001
Boolean functions

Digital
• What: expression in binary variables and
design
the operators AND, OR, NOT
Combina-
torial
• Priority:
circuits  parenthesis
Sequential
 NOT
circuits
 AND
FSMD  OR
design
• Eg. F1=xy+xy’z+x’yz
VHDL
 F1=1 when x=1 and y=1 or when x=1, y=0 and
z=1 or when x=0, y=1 and z=1; in all other cases
F1=0
 F1 consists of 3 AND-terms and 1 OR-term

1/51
©
R.Lauwereins
Imec 2001
Boolean functions

Digital • Realisation of F1=xy+xy’z+x’yz

design

Combina-
torial
x y z
circuits

Sequential
circuits

FSMD
design
F1
VHDL

1/52
©
R.Lauwereins
Imec 2001
Boolean functions

Digital • Truth table for F1=xy+xy’z+x’yz

design
 n variables  2n rows
Combina-  standard numbering
torial
circuits

Sequential
circuits
x y z
Row x y z F1
FSMD
design 0 0 0 0 0
1 0 0 1 0
VHDL 2 0 1 0 0
3 0 1 1 1
F1 4 1 0 0 0
5 1 0 1 1
6 1 1 0 1
7 1 1 1 1

1/53
©
R.Lauwereins
Imec 2001
Boolean functions

Digital
• Building up a truth table using standard
design
numbering:
Combina-
torial
circuits
X Y Z
Sequential 0 0 0
circuits
0 0 1
FSMD 0 1 0
design
0 1 1
VHDL
1 0 0
1 0 1
1 1 0
1 1 1

1/54
©
R.Lauwereins
Imec 2001
Boolean functions

Digital • Truth table for F1=xy+xy’z+x’yz

design
 numbering following the Gray code (two
Combina- consecutive rows only differ in 1 variable)
torial
circuits

Sequential
circuits x y z F1
0 0 0 0
FSMD
design
0 0 1 0
0 1 1 1
VHDL 0 1 0 0
1 1 0 1
1 1 1 1
1 0 1 1
1 0 0 0

1/55
©
R.Lauwereins
Imec 2001
Boolean functions

Digital
• Building up a truth table using the Gray
design
code:
Combina-
torial
circuits
X Y Z
Sequential 0 0 0
circuits
0 0 1
FSMD 0 1 1
design
0 1 0
VHDL
1 1 0
1 1 1
1 0 1
1 0 0

1/56
©
R.Lauwereins
Imec 2001
Boolean functions

Digital
• Complement of a Boolean function
design
F1’ =(xy+xy’z+x’yz)’
Combina- =(xy)’(xy’z)’(x’yz)’ (De Morgan)
torial
circuits =(x’+y’)(x’+y+z’)(x+y’+z’) (De Morgan)

Sequential
circuits  This gives us the opportunity to convert an AND-
OR implementation in an OR-AND implementation
FSMD (see next slide)
design

VHDL

1/57
©
R.Lauwereins
Imec 2001
Boolean functions
• Realisation as AND- • Realisation as OR-
Digital
design OR: F1=xy+xy’z+x’yz AND: F1=((x’+y’)
(x’+y+z’) (x+y’+z’))’
Combina-
torial
circuits

x y z x y z
Sequential
circuits

FSMD
design

VHDL F1 F1

1/58
©
R.Lauwereins
Imec 2001
Boolean functions

Digital
• Algebraic manipulation
design
F1 =xy+xy’z+x’yz =xy+xyz+xy’z+x’yz (absorption)
Combina- =xy+x(y+y’)z+x’yz (distributive)
torial
circuits =xy+x1z+x’yz (complement)
=xy+xz+x’yz (identity)
Sequential
circuits =xy+xyz+xz+x’yz (absorption)
FSMD
=xy+xz+(x+x’)yz (distributive)
design
=xy+xz+1yz (complement)
VHDL =xy+xz+yz (identity)
 This alternative form is cheaper (see next
slide)
 There does not exist a fixed rule to combine
theorems to guarantee a cheaper result
 Further slides will present a non-algebraic
method that always leads to the cheapest
1/59
solution
©
R.Lauwereins
Imec 2001
Boolean functions

Digital
• F1=xy+xy’z+x’yz • F1=xy+xz+yz
design

Combina-
torial x y z x y z
circuits

Sequential
circuits

FSMD F1 F1
design

VHDL

1/60
©
R.Lauwereins
Imec 2001
Contents of “Digital Design”

Digital
• Introduction to the course
design
• Data representation
Combina-
torial • Boolean algebra
circuits
 Axiomatic definition of Boolean algebra
Sequential  Theorems of Boolean algebra
circuits
 Boolean functions
FSMD  Canonical form
design
 Standard form
VHDL  The 16 functions of 2 variables
• Logical gates

1/61
©
R.Lauwereins
Imec 2001
Canonical form

Digital
• How do we translate a truth table into a
design
Boolean expression?
Combina-
torial
• Definition: a minterm is a Boolean
circuits function that is true in 1 row of the truth
Sequential
table and false elsewhere
circuits

FSMD
design Row x y z minterm Notation
0 0 0 0 x’y’z’ m0
VHDL 1 0 0 1 x’y’z m1
2 0 1 0 x’yz’ m2
3 0 1 1 x’yz m3
4 1 0 0 xy’z’ m4
5 1 0 1 xy’z m5
6 1 1 0 xyz’ m6
7 1 1 1 xyz m7

1/62
©
R.Lauwereins
Imec 2001
Canonical form
• A 1-minterm is a minterm for which the function
Digital
design equals 1; a 0-minterm is a minterm for which the
function equals 0
Combina-
torial • For F1=xy+xy’z+x’yz
circuits
Row x y z F1 1-minterm
Sequential 0 0 0 0 0 -
circuits
1 0 0 1 0 -
FSMD 2 0 1 0 0 -
design 3 0 1 1 1 m3=x’yz
4 1 0 0 0 -
VHDL
5 1 0 1 1 m5=xy’z
6 1 1 0 1 m6=xyz’
7 1 1 1 1 m7=xyz

• Each Boolean function can be expressed as the

sum of its 1-minterms :
F1=x’yz+xy’z+xyz’+xyz=m3+m5+m6+m7=(3,5,6,7)
1/63
©
R.Lauwereins
Imec 2001
Canonical form
• Dual definition: a maxterm is a Boolean function
Digital
design that is false in 1 row of the truth table and true
elsewhere
Combina-
torial
circuits
Row x y z maxterm Notation
Sequential
0 0 0 0 x+y+z M0
circuits
1 0 0 1 x+y+z’ M1
FSMD 2 0 1 0 x+y’+z M2
design
3 0 1 1 x+y’+z’ M3
4 1 0 0 x’+y+z M4
VHDL
5 1 0 1 x’+y+z’ M5
6 1 1 0 x’+y’+z M6
7 1 1 1 x’+y’+z’ M7

1/64
©
R.Lauwereins
Imec 2001
Canonical form
• A 0-maxterm is a maxterm for which the function
Digital
design equals 0; a 1-maxterm is a maxterm for which the
function equals 1
Combina-
torial • For F1=xy+xy’z+x’yz
circuits
Row x y z F1 0-maxterm
Sequential
circuits
0 0 0 0 0 M0=x+y+z
1 0 0 1 0 M1=x+y+z’
FSMD 2 0 1 0 0 M2=x+y’+z
design 3 0 1 1 1 -
4 1 0 0 0 M4=x’+y+z
VHDL
5 1 0 1 1 -
6 1 1 0 1 -
7 1 1 1 1 -

• Each Boolean function can be expressed as the

product of its 0-maxterms:
F1 =(x+y+z)(x+y+z’)(x+y’+z)(x’+y+z)
=M0M1M2M4=(0,1,2,4)
1/65
©
R.Lauwereins
Imec 2001
Contents of “Digital Design”

Digital
• Introduction to the course
design
• Data representation
Combina-
torial • Boolean algebra
circuits
 Axiomatic definition of Boolean algebra
Sequential  Theorems of Boolean algebra
circuits
 Boolean functions
FSMD  Canonical form
design
 Standard form
VHDL  The 16 functions of 2 variables
• Logical gates

1/66
 Standard form -- minimal
©
R.Lauwereins
Imec 2001

implementation in two layers

Digital
• In the canonical form each function is a
design
sum of 1-minterms or a product of 0-
Combina- maxterms
torial
circuits • Each minterm or maxterm contains all
Sequential
variables => expensive implementation
• The standard form is a sum of product
circuits

FSMD terms or a product of sum terms with the

design
smallest number of variables
VHDL
• A product term or sum term does not
necessarily contain all variables =>
cheaper implementation

1/67
 Standard form -- minimal
©
R.Lauwereins
Imec 2001

implementation in two layers

Digital
• Example 1
design F2 =xyz+xyz’+xy’z+xy’z’
Combina-
=xy(z+z’)+xy’(z+z’)
torial =xy+xy’
circuits
=x(y+y’)
Sequential =x
circuits
• Example 2
FSMD
design
F3 =xyz+xyz’+xy’z+x’yz+x’y’z’
=xyz+xyz’+xyz+xy’z+xyz+x’yz+x’y’z’
VHDL
=xy(z+z’)+x(y+y’)z+(x+x’)yz+x’y’z’
=xy+xz+yz+x’y’z’

1/68
 Standard form -- minimal
©
R.Lauwereins
Imec 2001

implementation in two layers

• The standard form is • A non-standard form in
Digital
design the cheapest more than two layers
implementation in two may be cheaper
Combina-
torial
layers • Eg. F2=x(y+z)+yz
circuits
• Eg. F2=xy+xz+yz
Sequential
circuits
xyz xyz
FSMD
design

VHDL
F2 F2

Multiplier: O(en) Multiplier: O(n2)

1/69
©
R.Lauwereins
Imec 2001
Contents of “Digital Design”

Digital
• Introduction to the course
design
• Data representation
Combina-
torial • Boolean algebra
circuits
 Axiomatic definition of Boolean algebra
Sequential  Theorems of Boolean algebra
circuits
 Boolean functions
FSMD  Canonical form
design
 Standard form
VHDL  The 16 functions of 2 variables
• Logical gates

1/70
©
R.Lauwereins
Imec 2001
The 16 functions of 2 variables
• Why 16 functions?
Digital
design

Combina-
torial
circuits x y F0 F1 F2 F15
0 0 0 0 0 1
Sequential
circuits 0 1 0 0 0 1
1 0 0 0 1 1
FSMD 1 1 0 1 0 1
design

VHDL There exist 4 possible combinations for x and y and

each combination can have a different functional
value. Each function F(x,y) is hence characterized
by 4 bits, i.e. the 4 functional values for xy, xy’, x’y
and x’y’. With 4 bits 24th different patterns for truth
table are possible. Hence, there are 24=16 different
functions F(x,y) possible, i.e. all possible
combinations of 4 bits.

1/71
©
R.Lauwereins
Imec 2001
The 16 functions of 2 variables

Digital Functional value

design for x,y
Name Symbol 00 01 10 11 Expression
Combina-
torial
Zero - 0 0 0 0 F0=0
circuits AND x·y 0 0 0 1 F1=xy
Inhibition x/y 0 0 1 0 F2=xy’
Sequential
circuits
Transfer - 0 0 1 1 F3=x
Inhibition y/x 0 1 0 0 F4=x’y
FSMD Transfer - 0 1 0 1 F5=y
design
XOR xy 0 1 1 0 F6=xy’+x’y
OR x+y 0 1 1 1 F7=x+y
VHDL
NOR xy 1 0 0 0 F8=(x+y)’
XNOR - 1 0 0 1 F9=xy+x’y’
Complement y’ 1 0 1 0 F10=y’
Implication - 1 0 1 1 F11=x+y’
Complement x’ 1 1 0 0 F12=x’
Implication - 1 1 0 1 F13=x’+y
NAND xy 1 1 1 0 F14=(xy)’
One - 1 1 1 1 F15=1
1/72
©
R.Lauwereins
Imec 2001
Contents of “Digital Design”

Digital
• Introduction to the course
design
• Data representation
Combina-
torial • Boolean algebra
circuits
• Logical gates
Sequential  Gates
circuits
 Non-functional properties
FSMD
design
 Implementation technologies

VHDL

1/73
©
R.Lauwereins
Imec 2001
Contents of “Digital Design”

Digital
• Introduction to the course
design
• Data representation
Combina-
torial • Boolean algebra
circuits
• Logical gates
Sequential  Gates
circuits
 Switching transistor
FSMD  Basic logical gates
design
 Gates with multiple inputs (fan-in)
VHDL  Multiple operators in a single gate
 Non-functional properties
 Implementation technologies

1/74
©
R.Lauwereins
Imec 2001
Contents of “Digital Design”

Digital
• Introduction to the course
design
• Data representation
Combina-
torial • Boolean algebra
circuits
• Logical gates
Sequential  Gates
circuits
Switching transistor
FSMD  Basic logical gates
design
 Gates with multiple inputs (fan-in)
VHDL  Multiple operators in a single gate
 Non-functional properties
 Implementation technologies

1/75
©
R.Lauwereins
Imec 2001
Switching transistor
n-MOS transistor
Digital
design

Combina- Isolator Metal

torial
circuits
Source Gate Drain
Sequential
circuits

FSMD
design n+ n+
VHDL p

1/76
©
R.Lauwereins
Imec 2001
Switching transistor
n-MOS transistor
Digital
design
Infinite number
Combina- of free electrons
torial
circuits
Vss Vss Vss
Sequential
circuits
Many free Many free
electrons electrons
FSMD
design n+ n+
VHDL p

D=Vss
Hardly any
G=Vss free electrons:
no conducting path
between Source
and Drain
S=Vss
1/77
©
R.Lauwereins
Imec 2001
Switching transistor
n-MOS transistor
Digital
design

Combina-
torial
circuits
Vss Vss
Vcc Vss
Sequential
circuits

FSMD
design n+ n+
VHDL p

D=Vss
Many free electrons
attracted by positive
G=Vcc gate voltage:
conducting channel
between Source
S=Vss and Drain
1/78
©
R.Lauwereins
Imec 2001
Switching transistor
p-MOS transistor
Digital
design

Similar construction, but ‘p’ and ‘n’ doping reversed

Combina-
torial
circuits

Sequential Conducts when Does not conduct when

circuits
gate voltage = Vss gate voltage = Vcc
FSMD
design

VHDL D=Vss D=Vss

G=Vss G=Vcc

S=Vss S=Vss

1/79
©
R.Lauwereins
Imec 2001
Contents of “Digital Design”

Digital
• Introduction to the course
design
• Data representation
Combina-
torial • Boolean algebra
circuits
• Logical gates
Sequential  Gates
circuits
 Switching transistor
FSMD Basic logical gates
design
 Gates with multiple inputs (fan-in)
VHDL  Multiple operators in a single gate
 Non-functional properties
 Implementation technologies

1/80
©
R.Lauwereins
Imec 2001
Basic logical gates

Digital
• Invertor
design
 F=x’, 2 transistors, relative propagation delay: 1
Combina-
torial
circuits
Vcc
Sequential
circuits

FSMD
design
x=0
x
x=1 F=1
F
F=0 x=0
x
x=1 F=1
F
F=0
VHDL

Vss

1/81
©
R.Lauwereins
Imec 2001
Basic logical gates
• Driver
Digital
design  F=x, 4 transistors, relative propagation-delay: 2; goal: higher
power drive
Combina-
torial
circuits
Vcc Vcc
Sequential
circuits

FSMD
design

x=0
x=1
x F=0
F=1
F x=0
x=1
x F=0
F=1
F
VHDL

Vss Vss

1/82
©
R.Lauwereins
Imec 2001
Basic logical gates

Digital
• NAND
design
 F=(xy)’, 4 TOR, relative propagation-delay: 1.4
Combina-
torial Vcc
circuits

Sequential
circuits x=0
x=1
x y=0
y=1
y

FSMD
design
F=1
F=0
F
VHDL
x=0
x=1
x F=1
F=0
F y=0
y=1
y

y=0
y=1
y x=0
x=1
x

Vss
1/83
©
R.Lauwereins
Imec 2001
Basic logical gates

Digital
• NOR
design
 F=(x+y)’, 4 TOR, relative propagation-delay: 1.4
Combina- Vcc
torial
circuits

Sequential y=0
y=1
y
circuits

FSMD
design
x=0
x=1
x

F=1
F=0
F
VHDL x
x=0
x=1 F=1
F=0
F

x=0
x=1
x y=0
y=1
y
y
y=0
y=1

Vss

1/84
©
R.Lauwereins
Imec 2001
Basic logical gates

Digital
• AND
design
 F=xy, 6 TOR, relative propagation-delay: 2.4
Combina-
Vcc
torial
circuits
Vcc

Sequential
circuits x y

FSMD
design F

VHDL
x y
F

y x
Vss

Vss
1/85
©
R.Lauwereins
Imec 2001
Basic logical gates

Digital
• OR
design
 F=x+y, 6 TOR, relative propagation-delay: 2.4
Combina- Vcc
torial
circuits
Vcc
Sequential y
circuits

FSMD
design
x

F
VHDL x F

x y
y

Vss
Vss

1/86
©
R.Lauwereins
Imec 2001
Basic logical gates
• XNOR
Digital  F=(xy)’, 12 TOR, Vcc
relative
design
propagation-
delay: 3.2

Combina-
y=0
y=1
y y’=1
y’=0
y’
torial
circuits
Vcc
cc

x=0
x=1
x x’=1
x’=0
x’
Sequential
x x’
x’=1
x’=0
x’=0
circuits
x
x=0
x=1 F=0
F=1
F
F=0
F=1
F
FSMD
design Vss
ss
y
y=0
y=1
x=0
x=1
x y=0
y=1
y
VHDL
Vcc
x y
y F
F
0 0
0 1
1 y’
y’=1
y’=0
0 1 0
y
1 0
1 0
0 0
0 x’=1
x’=0
x’ y’=1
y’=0
y’
1 1
1 1
1 Vss

1/87
Vss
©
R.Lauwereins
Imec 2001
Basic logical gates
• XOR
Digital  F=(xy), 12 TOR, Vcc
relative
design
propagation-
delay: 3.2

Combina-
y’ y
torial
circuits
Vcc

x x’
Sequential
x x’
circuits
x F
F
FSMD
design Vss
y
x y’
VHDL
Vcc
x y F
0 0 0 y’
y
0 1 1
1 0 1 x’ y
1 1 0 Vss

1/88
Vss
©
R.Lauwereins
Imec 2001
Contents of “Digital Design”

Digital
• Introduction to the course
design
• Data representation
Combina-
torial • Boolean algebra
circuits
• Logical gates
Sequential  Gates
circuits
 Switching transistor
FSMD  Basic logical gates
design
Gates with multiple inputs (fan-in)
VHDL  Multiple operators in a single gate
 Non-functional properties
 Implementation technologies

1/89
©
R.Lauwereins
Imec 2001
Gates with multiple inputs (fan-in)
• 3-input NAND
Digital  F=(xyz)’, 6 TOR, Vcc
relative
design
propagation-
delay: 1.8

Combina-
torial x y z
circuits

Sequential
circuits

z F
FSMD
design

VHDL
F y
x
y
z
x

Vss
1/90
©
R.Lauwereins
Imec 2001
Contents of “Digital Design”

Digital
• Introduction to the course
design
• Data representation
Combina-
torial • Boolean algebra
circuits
• Logical gates
Sequential  Gates
circuits
 Switching transistor
FSMD  Basic logical gates
design
 Gates with multiple inputs (fan-in)
VHDL Multiple operators in a single gate
 Non-functional properties
 Implementation technologies

1/91
©
R.Lauwereins
Imec 2001
Multiple operators in a single gate
• 2-wide 2-input
AND-OR-Invert Vcc
Digital  F=(xy + zw)’, 8 TOR,
design relative
propagation-
delay: 2.2

Combina-
z w
torial
circuits

Sequential
circuits x y
x
FSMD
design
y F
F
VHDL
z y w
w

x z

1/92
Vss
©
R.Lauwereins
Imec 2001
Multiple operators in a single gate
• 2-wide 2-input
OR-AND-Invert Vcc
Digital  F=((x+y)(z+w))’,
8 TOR,
design relative
propagation-
delay: 2.2

Combina-
y w
torial
circuits

x z
Sequential
circuits

F
FSMD
design
x
z w
VHDL y
F
z
w x y

1/93
Vss
©
R.Lauwereins
Imec 2001
Contents of “Digital Design”

Digital
• Introduction to the course
design
• Data representation
Combina-
torial • Boolean algebra
circuits
• Logical gates
Sequential  Gates
circuits
 Non-functional properties
FSMD  Logical voltage levels and noise margin
design
 Fan-out
VHDL  Power dissipation
 Propagation delay
 Implementation technologies

1/94
©
R.Lauwereins
Imec 2001
Contents of “Digital Design”

Digital
• Introduction to the course
design
• Data representation
Combina-
torial • Boolean algebra
circuits
• Logical gates
Sequential  Gates
circuits
 Non-functional properties
FSMD Logical voltage levels and noise margin
design
 Fan-out
VHDL  Power dissipation
 Propagation delay
 Implementation technologies

1/95
 Logic voltage levels and noise
©
R.Lauwereins
Imec 2001

margin
Digital
• For CMOS and TTL, 0V corresponds to the logical
design ‘0’ and 5V to ‘1’ (ideal and in steady state)
• Realistically and during transition for TTL
Combina-
torial invertor:
circuits

Sequential
circuits
Vout
FSMD 5
design
Variation function of:
High - temperature
VHDL
- power supply voltage
2.4 - manufacturing

0.4
Low
0
0 0.8 2.0 5 Vin
1/96 Low High
 Logic voltage levels and noise
©
R.Lauwereins
Imec 2001

margin
Digital
• TTL guarantees a low output level
design
between 0V and 0.4V (=VOL) and
Combina- recognizes voltages between 0V and 0.8V
(=VIL) as logic ‘0’
torial
circuits

Sequential • Noise up to 0.4V peak between output

circuits
and next input are interpreted correctly
FSMD
design
• The noise margin is hence VIL-VOL=0.4V
• TTL guarantees a high output level
VHDL
between 2.4V (=VOH) and 5V and
recognizes voltages between 2.0V (=VIH)
and 5V as logic ‘1’
• Noise up to 0.4V peak between output
and next input are interpreted correctly
1/97
• The noise margin is hence VOH-VIH=0.4V
 Logic voltage levels and noise
©
R.Lauwereins
Imec 2001

margin
Digital
• Graphical representation of noise margin:
design

Combina-
torial
circuits
Vcc Vcc
High
Sequential
VOH High
circuits Margin VIH

FSMD
design

VHDL
VIL
VOL Margin
Low
Low
Vss Vss

Output Input

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©
R.Lauwereins
Imec 2001
Contents of “Digital Design”

Digital
• Introduction to the course
design
• Data representation
Combina-
torial • Boolean algebra
circuits
• Logical gates
Sequential  Gates
circuits
 Non-functional properties
FSMD  Logical voltage levels and noise margin
design
Fan-out
VHDL  Power dissipation
 Propagation delay
 Implementation technologies

1/99
 Fan-out: ‘current driven’
©
R.Lauwereins
Imec 2001

technologies cf. TTL, ECL, ...

Digital
• Fan-out: maximum number of inputs that
design
may be connected to a single output
Combina-
torial
• Depends on the current that may be
circuits delivered by the driving gate (source) (IOH)
Sequential
w.r.t. the current consumed by the driven
circuits
gate (IIH) and on the current sinked by the
FSMD driving gate (sink) (IOL) w.r.t. the current
design
delivered by the driven gate (IIL)
VHDL
• Fan-out = min(IOH/IIH,IOL/IIL)
IIH IIL

IOH IOL

1/100
 Fan-out: ‘charge driven’
©
R.Lauwereins
Imec 2001

technologies cf. CMOS

Digital
• Fan-out: maximum number of inputs that
design
may be connected to a single output
Combina- • Depends on the current that may be
torial
circuits sourced resp. sinked by the driving gate
Sequential
(IOH resp. IOL) w.r.t. the capacity of the
circuits
connected inputs and the connecting wire
FSMD and to the switching time allowed
design
• I=dQ/dt=C.dV/dt=C.f.V => determines
VHDL maximum switching frequency
• e.g. based on realistic values for Xilinx
Virtex:
 10 pF input capacity, 20 mA drive current, 0.8
pF/cm PCB connect, Vcc=3.3 V
 For fan-out=3 and 10 cm PCB connect:
C=3*10+0.8*10=38 pF and switching frequency
1/101
= I/(C.V)=20 mA/(38 pF * 3.3 V)=160 MHz
©
R.Lauwereins
Imec 2001
Contents of “Digital Design”

Digital
• Introduction to the course
design
• Data representation
Combina-
torial • Boolean algebra
circuits
• Logical gates
Sequential  Gates
circuits
 Non-functional properties
FSMD  Logical voltage levels and noise margin
design
 Fan-out
VHDL Power dissipation
 Propagation delay
 Implementation technologies

1/102
©
R.Lauwereins
Imec 2001
Power dissipation

Digital
• TTL dissipates continuously
design
 P=VCC*ICC10mW/gate
Combina-  1 million gates: 10 KW!!
torial
circuits  Only used when high voltages or large currents
are needed (busdrivers, …)
Sequential
circuits • CMOS dissipates only while switching
 P=C.f.V2 since I=C.f.V
FSMD
design  C: proportional to chip area (trend: increase)
 f: trend: steep increase: 1MHz  1 GHz
VHDL
 V: trend: steady decrease: 5  3.3  2.5  1.8 
1.5  1.2  0.9
 Virtex example: P=38 pF*160 MHz*(3.3 V)2=
66 mW per switching pin; assuming 200 pins, half
of which switch concurrently, gives 6.6 W for
driving the external pins
 Advanced microprocessors: 40W  Cooling!!!
1/103  Is currently the limiting design factor
©
R.Lauwereins
Imec 2001
Contents of “Digital Design”

Digital
• Introduction to the course
design
• Data representation
Combina-
torial • Boolean algebra
circuits
• Logical gates
Sequential  Gates
circuits
 Non-functional properties
FSMD  Logical voltage levels and noise margin
design
 Fan-out
VHDL  Power dissipation
Propagation delay
 Implementation technologies

1/104
©
R.Lauwereins
Imec 2001
Propagation delay
Rise Fall
time time
Digital
design Rise time > Fall time

Combina- 90%
torial
circuits

50%
Sequential
circuits
10%
FSMD
design

VHDL 90%

50%

10%
Propagation delay:
tPLH tPHL tP=(tPLH+tPHL)/2
1/105
©
R.Lauwereins
Imec 2001
Contents of “Digital Design”

Digital
• Introduction to the course
design
• Data representation
Combina-
torial • Boolean algebra
circuits
• Logical gates
Sequential  Gates
circuits
 Non-functional properties
FSMD
design
 Implementation technologies
 SSI, MSI, LSI, VLSI
VHDL  Custom design, standard cell design
 Gate array
 PLA, PLD, FPGA

1/106
©
R.Lauwereins
Imec 2001
Contents of “Digital Design”

Digital
• Introduction to the course
design
• Data representation
Combina-
torial • Boolean algebra
circuits
• Logical gates
Sequential  Gates
circuits
 Non-functional properties
FSMD
design
 Implementation technologies
SSI, MSI, LSI, VLSI
VHDL  Custom design, standard cell design
 Gate array
 PLA, PLD, FPGA

1/107
©
R.Lauwereins
Imec 2001
SSI, MSI, LSI, VLSI (I)

Digital
• SSI: Small Scale Integration
design
 < 10 gates per package
Combina-  gates directly connected to package pins
torial
circuits  designed using transistor level design
 used using gate level design
Sequential
circuits
• MSI: Medium Scale Integration
FSMD  10 - 100 gates per package
design
 registers, adders, parity generators, …
VHDL  designed using gate level design
 used using RTL design
• LSI: Large Scale Integration
 100 - 10K gates per package
 controllers, data paths
 designed using RTL design
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 used using behavioral level design
©
R.Lauwereins
Imec 2001
SSI, MSI, LSI, VLSI (II)

Digital
• VLSI: Very Large Scale Integration
design
 10K - 1M gates per package
Combina-  memory, microprocessor, microcontroller, FFT
torial
circuits  designed using behavioral level design
 used using system level design
Sequential
circuits
• ULSI: Ultra Large Scale Integration???
FSMD  1M - ?? Gates per package
design
 2 controllers, 20 DSP processors, 16 Mbyte
VHDL memory, 10 accelerators, 1 Mgate FPGA,
Analog interface, RF
 designed using system level design
 only one chip needed for complete
application ??

1/109
©
R.Lauwereins
Imec 2001
Contents of “Digital Design”

Digital
• Introduction to the course
design
• Data representation
Combina-
torial • Boolean algebra
circuits
• Logical gates
Sequential  Gates
circuits
 Non-functional properties
FSMD
design
 Implementation technologies
 SSI, MSI, LSI, VLSI
VHDL Custom design, standard cell design
 Gate array
 PLA, PLD, FPGA

1/110
©
R.Lauwereins
Imec 2001
Custom design

Digital
• Each transistor and each connection is
design
designed individually as a set of
Combina- rectangles.
torial
circuits • Excellent for optimal design of library
Sequential
elements that are re-used multiple times
• Companies design and sell such
circuits

FSMD optimized libraries

design
• Has to be completely re-done each time
VHDL
technology changes (every 18 months!)

1/111
©
R.Lauwereins
Imec 2001
Standard cell design

Digital
• Library of standard cells
design
 each cell is a gate
Combina-  standard height, variable width, interleaved by
torial
circuits
routing channels
 all inputs at the top, all outputs at the bottom
Sequential
circuits • Faster design of more complex building
FSMD
blocks
design
• Silicon foundries design and sell such
VHDL optimized libraries for their processing
technology

Placement and routing

1/112
©
R.Lauwereins
Imec 2001
Standard cell design

Digital
• Design Flow
design

Combina- Design entry Simulation

torial
circuits

Sequential
circuits Placement

FSMD
design
Routing Timing simulation
VHDL

Fabrication: n masks Testing

1/113
©
R.Lauwereins
Imec 2001
Contents of “Digital Design”

Digital
• Introduction to the course
design
• Data representation
Combina-
torial • Boolean algebra
circuits
• Logical gates
Sequential  Gates
circuits
 Non-functional properties
FSMD
design
 Implementation technologies
 SSI, MSI, LSI, VLSI
VHDL  Custom design, standard cell design
Gate array
 PLA, PLD, FPGA

1/114
©
R.Lauwereins
Imec 2001
Gate array design

Digital
• Two-dimensional grid of identical gates
design
 each cell is for example a 3-input NAND gate
Combina-  standard height, standard width, interleaved by
torial
circuits
routing channels
 all inputs at the top, all outputs at the bottom
Sequential
circuits • Cheaper:
FSMD
 Only the last metallisation layer is project
design specific
VHDL

1/115
©
R.Lauwereins
Imec 2001
Gate array design

Digital
• Design Flow
design

Combina- Design entry Simulation

torial
circuits

Map all functions to

Sequential
circuits Technology mapping the available 3-input
NANDs
FSMD
design
Placement
VHDL

Routing Timing simulation

Fabrication: 1 mask Testing

1/116
©
R.Lauwereins
Imec 2001
Contents of “Digital Design”

Digital
• Introduction to the course
design
• Data representation
Combina-
torial • Boolean algebra
circuits
• Logical gates
Sequential  Gates
circuits
 Non-functional properties
FSMD
design
 Implementation technologies
 SSI, MSI, LSI, VLSI
VHDL  Custom design, standard cell design
 Gate array
PLA, PLD, FPGA

1/117
©
R.Lauwereins
Imec 2001
Field-programmable design

Digital
• Fuse programmable
design
 One time customer programmable by selectively
Combina-
blowing fuses
torial
circuits
 PLA: Programmable Logic Array
 PLD: Programmable Logic Device
Sequential
circuits
 CPLD: Complex PLD
• SRAM based
FSMD
design  FPGA: Field Programmable Gate Array (see
laboratory sessions)
VHDL
• Properties:
 Excellent for prototypes
 Excellent for medium volumes (<100K
pieces/year)
 For SRAM based: reconfiguration (static or
dynamic) possible
1/118
 2 Mgates @ 200 MHz (in 2000)
©
R.Lauwereins
Imec 2001
Field-programmable design

Digital
• PLA
design

Combina-
torial
circuits

Sequential
circuits

FSMD
design

VHDL

1/119
©
R.Lauwereins
Imec 2001
Field-programmable design
• PLD
Digital
design

Combina-
torial
circuits

Sequential
circuits

FSMD
design

VHDL

D D

1/120
©
R.Lauwereins
Imec 2001
Field-programmable design

Digital
• CPLD
design

Combina- O I/O I/O O

torial
circuits

Sequential AND-OR AND-OR

circuits Plane Plane

FSMD
design
Switch matrix
VHDL

AND-OR AND-OR
Plane Plane

O I/O I/O O

1/121
©
R.Lauwereins
Imec 2001
Field-programmable design

Digital
• XC95216
design
 6 Functional blocks (36V18 each)
Combina-  Flash programmable
torial
circuits

Sequential
circuits

FSMD
design

VHDL

1/122
©
R.Lauwereins
Imec 2001
Field-programmable design
• FPGA: XC40xx
Direct
Routing connections
viaLong
switching
lines matrices
Digital
design
I/O I/O I/O I/O
Combina-
torial
I/O
circuits
SM SM SM SM
Sequential
circuits

CLB CLB CLB

FSMD
design

VHDL
I/O

SM SM SM SM

CLB CLB CLB

I/O

SM SM SM SM
1/123
©
R.Lauwereins
Imec 2001
Field-programmable design

Digital
design

Combina-
torial
circuits

Sequential
circuits

FSMD
design

VHDL

1/124
©
R.Lauwereins
Imec 2001
Field-programmable design

Digital
• FPGA: Configurable Logic Block CLB
design

Combina-
torial
circuits
16x1 G
LUT: GQ
FF
Sequential Bool-function
circuits of 4
G
variables
FSMD
design

VHDL 16x1
F
LUT: FQ
FF
Bool-function
of 4
variables F

1/125
©
R.Lauwereins
Imec 2001
Field-programmable design

Digital
design

Combina-
torial
circuits

Sequential
circuits

FSMD
design

VHDL

1/126
©
R.Lauwereins
Imec 2001
Field-programmable design

Digital
• FPGA: Switching Matrix SM
design
Pass
Combina-
TOR
torial
circuits

Sequential
circuits

FSMD
design

VHDL

1/127
©
R.Lauwereins
Imec 2001
Field programmable design

Digital
• Design Flow
design

Combina- Design entry Simulation

torial
circuits

Sequential
circuits Technology mapping

FSMD
design
Placement
VHDL

Routing Timing simulation

Downloading Testing

1/128