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DEPpart5

DEPpart5

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Published by nguyenhainam910

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Published by: nguyenhainam910 on Apr 13, 2010
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10/25/2011

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 © R.LauwereinsImec 2001
DigitaldesignCombina-torialcircuitsSequentialcircuitsFSMDdesignVHDL
5/1
Course contents
Digital designCombinatorial circuits: without statusSequential circuits: with statusFSMD design: hardwired processors
Language based HW design: VHDL
 
 © R.LauwereinsImec 2001
DigitaldesignCombina-torialcircuitsSequentialcircuitsFSMDdesignVHDL
5/2
Language based HW design:a VHDL primer 
IntroductionA first look at VHDLSignals and data typesVHDL operatorsConcurrent versus sequentialstatementsSequential construction statementsHigher performance, less portability:e.g. synthesis issues for Xilinx
 
 © R.LauwereinsImec 2001
DigitaldesignCombina-torialcircuitsSequentialcircuitsFSMDdesignVHDL
5/3
Language based HW design:a VHDL primer 
IntroductionA first look at VHDLSignals and data typesVHDL operatorsConcurrent versus sequentialstatementsSequential construction statementsHigher performance, less portability:e.g. synthesis issues for Xilinx

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