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MIPS Architecture For Programmers_vol3

MIPS Architecture For Programmers_vol3

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Published by Jet Doan
MIPS32™ Architecture For Programmers Volume III: The MIPS32™ Privileged Resource Architecture
MIPS32™ Architecture For Programmers Volume III: The MIPS32™ Privileged Resource Architecture

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Published by: Jet Doan on Apr 14, 2010
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12/23/2012

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Document Number: MD00090Revision 0.95March 12, 2001MIPS Technologies, Inc.1225 Charleston RoadMountain View, CA 94043-1353
MIPS32™ Architecture For ProgrammersVolumeIII: The MIPS32™ Privileged ResourceArchitecture
 
Copyright © 2001 MIPS Technologies, Inc. All rights reserved.Unpublished rights reserved under the Copyright Laws of the United States of America.This document contains information that is proprietary to MIPS Technologies, Inc. (“MIPS Technologies”). Anycopying,modifyingoruseofthisinformation(inwholeorinpart)whichisnotexpresslypermittedinwritingbyMIPSTechnologiesoracontractually-authorizedthirdpartyisstrictlyprohibited.Ataminimum,thisinformationisprotectedunder unfair competition laws and the expression of the information contained herein is protected under federalcopyright laws. Violations thereof may result in criminal penalties and fines.MIPSTechnologiesoranycontractually-authorizedthirdpartyreservestherighttochangetheinformationcontainedinthisdocumenttoimprovefunction,designorotherwise.MIPSTechnologiesdoesnotassumeanyliabilityarisingoutof theapplicationoruseofthisinformation.Anylicenseunderpatentrightsoranyotherintellectualpropertyrightsownedby MIPS Technologies or third parties shall be conveyed by MIPS Technologies or any contractually-authorized thirdparty in a separate license agreement between the parties.The information contained in this document constitutes one or more of the following: commercial computer software,commercialcomputersoftwaredocumentationorothercommercialitems.Iftheuserofthisinformation,oranyrelateddocumentationofanykind,includingrelatedtechnicaldataormanuals,isanagency,department,orotherentityoftheUnited States government (“Government”), the use, duplication, reproduction, release, modification, disclosure, ortransfer of this information, or any related documentation of any kind, is restricted in accordance with FederalAcquisitionRegulation12.212forcivilianagenciesandDefenseFederalAcquisitionRegulationSupplement227.7202formilitaryagencies.TheuseofthisinformationbytheGovernmentisfurtherrestrictedinaccordancewiththetermsof the license agreement(s) and/or applicable contract terms and conditions covering this information from MIPSTechnologies or any contractually-authorized third party.MIPS,R3000,R4000,R5000,R8000andR10000areamongtheregisteredtrademarksofMIPSTechnologies,Inc.,andR4300, R20K, MIPS16, MIPS32, MIPS64, MIPS-3D, MIPS I, MIPS II, MIPS III, MIPS IV, MIPS V, MDMX,SmartMIPS,4K,4Kc,4Km,4Kp,5K,5Kc,20K,20Kc,EC,MGB,SOC-it,SEAD,YAMON,ATLAS,JALGO,CoreLVand MIPS-based are among the trademarks of MIPS Technologies, Inc.All other trademarks referred to herein are the property of their respective owners.
MIPS32™ Architecture For Programmers VolumeIII, Revision 0.95
 
MIPS32Architecture For Programmers VolumeIII, Revision 0.95i
Table of Contents
Chapter 1About This Book........................................................................................................................................................11.1Typographical Conventions...........................................................................................................................................11.1.1Italic Text.............................................................................................................................................................11.1.2Bold Text.............................................................................................................................................................11.1.3Courier Text.........................................................................................................................................................11.2UNPREDICTABLE and UNDEFINED........................................................................................................................21.2.1UNPREDICTABLE.............................................................................................................................................21.2.2UNDEFINED.......................................................................................................................................................21.3Special Symbols in Pseudocode Notation......................................................................................................................21.4For More Information....................................................................................................................................................5Chapter 2The MIPS32 Privileged Resource Architecture.........................................................................................................72.1Introduction....................................................................................................................................................................72.2The MIPS Coprocessor Model.......................................................................................................................................72.2.1CP0 - The System Coprocessor...........................................................................................................................72.2.2CP0 Registers.......................................................................................................................................................7Chapter 3MIPS32 Operating Modes..........................................................................................................................................93.1 Debug Mode..................................................................................................................................................................93.2Kernel Mode..................................................................................................................................................................93.3Supervisor Mode............................................................................................................................................................93.4User Mode......................................................................................................................................................................9Chapter 4Virtual Memory........................................................................................................................................................114.1Terminology.................................................................................................................................................................114.1.1Address Space....................................................................................................................................................114.1.2Segment and Segment Size................................................................................................................................114.1.3Physical Address Size (PABITS).......................................................................................................................114.2Virtual Address Spaces................................................................................................................................................114.3Compliance..................................................................................................................................................................144.4Access Control as a Function of Address and Operating Mode..................................................................................144.5Address Translation and Cache Coherency Attributes for the kseg0 and kseg1 Segments.........................................154.6Address Translation for the kuseg Segment when StatusERL = 1..............................................................................164.7Special Behavior for the kseg3 Segment when DebugDM = 1...................................................................................164.8TLB-Based Virtual Address Translation.....................................................................................................................164.8.1Address Space Identifiers (ASID).....................................................................................................................164.8.2TLB Organization..............................................................................................................................................174.8.3Address Translation...........................................................................................................................................17Chapter 5Interrupts and Exceptions.........................................................................................................................................215.1Interrupts......................................................................................................................................................................215.2Exceptions....................................................................................................................................................................225.2.1Exception Vector Locations...............................................................................................................................225.2.2General Exception Processing...........................................................................................................................235.2.3EJTAG Debug Exception..................................................................................................................................245.2.4Reset Exception.................................................................................................................................................255.2.5Soft Reset Exception..........................................................................................................................................265.2.6 Non Maskable Interrupt (NMI) Exception.......................................................................................................275.2.7Machine Check Exception.................................................................................................................................285.2.8Address Error Exception....................................................................................................................................285.2.9TLB Refill Exception.........................................................................................................................................295.2.10TLB Invalid Exception....................................................................................................................................29

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