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Computer Design

Computer Design



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Published by ElliottRosenthal
Notes based on Cambridge Universities first year course in Computer Design.
Notes based on Cambridge Universities first year course in Computer Design.

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Published by: ElliottRosenthal on May 18, 2008
Copyright:Traditional Copyright: All rights reserved


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Computer Design
Part 1B, Dr S.W. Moore
The aims of this course are to introduce the hardware/software interface models and the hardwarestructures used in designing computers. The first seven lectures are concerned with the hardware/softwareinterface and cover the programmer's model of the computer. The last nine lectures look at hardwareimplementation issues at a register transfer level.
Introduction to the course and some background history.
Historic machines. EDSAC versus Manchester Mark I.
Introduction to RISC processor design and the MIPS instruction set.
MIPS tools and code examples.
Operating system support including memory hierarchy and management.
Intel x86 instruction set.
 Java Virtual Machine.
Memory hierarchy (caching).
Executing instructions. An algorithmic viewpoint.
Basic processor hardware, pipelining and hazards. [2 lectures]
Verilog implementation of a MIPS processor. [3 lectures]
Internal and external communication.
Data-flow and comments on future directions.
At the end of the course students should:
1.be able to read assembler given a guide to the instruction set and be able to write short pieces of assembler if given aninstruction set or asked to invent an instruction set2.understand the differences between RISC and CISC assembler3.understand what facilities a processor provides to support operating systems, from memory management to softwareinterrupts4.understand memory hierarchy including different cache structures5.appreciate the use of pipelining in processor design6.understand the communications structures, from buses close to the processor, to peripheral interfaces7.have an appreciation of control structures used in processor design8.have an appreciation of how to implement a processor in Verilog
Instruction Sets
Objective 1
An accumulator is a registerin which intermediatearithmetic and logicresults are stored. The characteristic which distinguishes one register as being the accumulator of a computer architectureis that the accumulator is used as an implicitoperandfor arithmetic instructions.For instance, a computer might have an instruction like:
This instruction would add the value read from the memorylocation at memaddress to the value from the accumulator, placing the result in the accumulator.
A processor register is a small amount ofstorageavailable on the CPUwhose contents can be accessed more quickly than storage available elsewhere. Moving data from main memory into registers, operating onthem, then moving the result back into main memory is common—a so-calledload-store architecture.
A stack machines memory takes the form of one or more stacks. In addition, a stack machine can also refer to a real or simulated machine with a "0-operand"instruction set. In such a machine, most instructionsimplicitly operate on values at the top of the stack and replace those values with the result. Typically suchmachines also have a "load" and a "store" instruction that reads and writes to arbitrary RAM locations.A stack machine will often be more simple to program and more reliable to run than other machines.Writing compilers for stack based machines is also comparatively simple, as they have fewer exceptionalcases to complicate matters. Since running compilers can take up a significant percentage of machineresources, building a machine that can have an efficient compiler is important.
A stack based machine instruction is smaller than one that’s register based since there is no need tospecify operand addresses. This nearly always leads to dramatically smaller compiled programs.A given task can often be expressed using fewer register machine instructions than stack ones.
Stack Machine:
a = b + c might be translated as
Register Machine:
The same code would be a single instruction
ADD a, b, c

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