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4-Homeworks_HW_2_coe_081_202_02

4-Homeworks_HW_2_coe_081_202_02

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Published by: kstu1112 on Apr 21, 2010
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07/01/2014

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Dr. Ashraf S. Hasan Mahmoud Dec 14
th
, 2008HW_2_coe_081_202_02.doc Page 1 of 3
 KFUPM - COMPUTER ENGINEERING DEPARTMENT 
COE-202 – Fundamentals of Computer Engineering
Assignment # 2: Due Sunday January 4
th
, 2008 – in class.Problem 1) (20 points)
Simplify the following Boolean functions to the form of sum-of- products by finding all prime implicants and essential prime implicants and applying theselection rule:a) F(W,X,Y,Z) =
Σ
m(0,1,2,6,8,9,10,13) b) F(A,B,C,D) =
Π
M(1,3,5,6,7,9,10,11,14)
Problem 2) (20 points)
Simplify the following expressions in (1) sum-of-products and(2) product-of-sums forms. Use the K-map method for the simplification:a) AC’ + B’D + A’CD + ABCD b) (A’ + B’ + D) (A’ + D’) (A + B + D’) (A + B’ + C + D)
Problem 3) (30 points)
It is required to implement a 4-bit ripple carry adder usingLogiSim:a) Implement the full adder circuit explained in class and shown in Figure P3a. Make thisas an “FA” circuit added to your project. b) Add another circuit called “4-bit Ripple Carry Adder”. Use the FA block to constructthe 4-bit carry adder. Test your new circuit with few examples and verify that it is performing the required function.Provide screenshots for part (a) and part (b).
Hint:
follow the instructions given in class and illustrated inhttp://ozark.hendrix.edu/~burch/logisim/docs/2.1.0/guide/subcirc/using.html 
Half adder 
A
i
B
i
C
i+1
S
i
C
iHalf adder Half adder 
A
i
B
i
C
i+1
S
 
i
C
iHalf adder 
 
FA
C
i
S
i
A
i
B
i
C
i+1
FA
C
i
S
i
A
i
B
i
C
i+1
 Figure P3a: Full adder circuit. Figure P3b: Full adder block diagram.
Problem 4) (50 points)
It is required to implement a 4-bit Carry Lookahead Adder (CLA) using LogiSim:a) Implement the partial adder circuit explained in class and shown in Figure P4a. Makethis as a “PA” circuit added to your project. b) Add another circuit called “4-bit Carry Lookahead Adder”. Use the PA block toconstruct the 4-bit carry look ahead adder plus the required logic (AND and OR gates) to

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