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Floating Point Arithmetic final

Floating Point Arithmetic final

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Published by Manoj Kumar Naga
implementation of floating point arithmetic in fpga with lcd interfacing..complete project with simulations.
implementation of floating point arithmetic in fpga with lcd interfacing..complete project with simulations.

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Published by: Manoj Kumar Naga on Apr 24, 2010
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01/15/2013

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FLOATING POINT ARITHMETIC ON FPGA 
3DJH_
PROJECT REPORTON
IMPLEMENTATION OF FLOATING POINTARITHMETIC ON FPGA
DIGITAL SYSTEM ARCHITECTURE
WINTER SEMESTER-2010
BY SUBHASH C (200911005) A N MANOJ KUMAR (200911030)PARTH GOSWAMI (200911049)
 
FLOATING POINT ARITHMETIC ON FPGA 
3DJH_
 ACKNOWLEDGEMENT:
We would like to express our deep gratitude to Dr.Rahul Dubey, who notonly gave us this opportunity to work on this project, but also guided andencouraged us throughout the course. He and TAs of the course, NeerajChasta and Purushothaman, patiently helped us throughout the project. Wetake this as opportunity to thank them and our classmates and friends forextending their support and worked together in a friendly learningenvironment. And last but not the least, we would like to thank non-teachinglab staff who patiently helped us to understand that all kits were workingproperly.BySubhash CA N Manoj KumarParth Goswami
 
FLOATING POINT ARITHMETIC ON FPGA 
3DJH_
 
CONTENTS
1
. PROBLEM STATEMENT 42. ABSTRACT 43. INTRODUCTION 53.
1
. FLOATING POINT FORMAT USED 63.2. DETECTION OF SPECIAL INPUTS 64. FLOATING POINT ADDER/SUBTRACTOR 85. FLOATING POINT MULTIPLIER 95.
1
. ARCHITECTURE FOR FLOATING POINT MULTIPLICATION
10
 5.2. DESIGNED 4 * 4 BIT MULTIPLIER.
1
26. VERIFICATION PLAN
1
47. SIMULATION RESULTS & RTL SCHEMATICS
1
58. FLOOR PLAN OF DESIGN & MAPPING REPORT 2
1
 9. POWER ANALYSIS USING XPOWER ANALYZER 25
10
. CONCLUSION 26
11
. FUTURE SCOPE 26
1
2. REFERENCES 27
1
3. APPENDIX 28

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Ajay Rathor added this note
this is good
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Nupur Gupta added this note
hello i am also working on this project n i need your help to design testbench for this in which all the module accept same value.
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