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# Fhdl Lab Answers

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verilog
verilog

Published by: Pavan Kumar P N on May 14, 2010

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07/25/2013

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FHDL LAB QUESTION BANK
1. a). Write a verilog code to simulate all the basic gates.b). Write a verilog code to synthesize a 4 bit up counter with synchronous resetand display the result on seven segment display.
module upcounter(clk,rst,Q,nQ);input clk,rst;output[3:0]Q,nQ;reg[3:0]Q;reg[15:0]clk1 = 16’d0;assign nQ=~Q;always@(posedge clk)clk1=clk1+1;always@(posedge clk1[15])beginif(reset)Q<=4’b0000;else Q<= Q+1;endendmodule
2. Write a verilog code to simulate i) 2 to 4 decoderii) 8 to 3 encoder (without priority)
module encoder (en,x,y);output [2:0]y;input en;input[7:0]x:reg[2:0]y;always @ (en,x)begin if (en ==1)y = 3’d0;elsecase(x)8’b00000001: y = 3’d0;

8’b00000010: y = 3’d1;8’b00000100: y = 3’d2;8’b00001000: y = 3’d3;8’b00010000: y = 3’d4;8’b00100000: y = 3’d5;8’b01000000: y = 3’d6;8’b10000000: y = 3’d7;default: y = 3’bxxx;endcaseendendmodule
iii) 1 to 4 demux (behavioral modeling)
module demux1(z,a,b,en);input a,b,en;output[3:0]z;reg z;always @ (a or b or en)case({en,a,b})default: z = 4’b1111;3’b100: z = 4’b1110;3’b110: z = 4’b1101;3’b101: z = 4’b1011;3’b111: z = 4’b0111;endcaseendmodule
3. Write a structural verilog code for a full adder using 2 half adders andsynthesize the same on to fpga board.
endmodule
4. Write the verilog code for a Full Adder, that takes in three 1-bit inputs, a, b andcarryin, and gives sum and carryout 1-bit outputs. Write the code for a testbenchfor the adder, and give appropriate inputs to test all possible combinations.