Professional Documents
Culture Documents
Presented By-
Siddharth
Chauhan
INTRODUCTION
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 I I I I I I
2 1 1 O O O O O O
I - input O - output
TIMER
The Timer is a 14 bit down-counter that counts the “timer input”
pulses and provides either a square wave or pulse when the
terminal count is reached.
Address for the Low order byte of register : XXXXX100
Address for the high order byte of register : XXXXX101
To Program the Timer, the COUNT LENGTH REGISTER is loaded
first, one byte at a time, by selecting the timer addresses.
Bits 0~13 specify the count of next count
Bits 14~15 specify the Timer Output Mode.
The value of the count length register may have any value
from 2H through 3FFFH on bits 0~13.
MSB:
M2 M1 T13 T12 T11 T10 T9 T8
LSB:
T7 T6 T5 T4 T3 T2 T1 T0
TIMER MODES
There are 4 basic Timer Modes which may be defined by M1 and M2 :-
0 0: Single square wave of wavelength TC/2 (TC/2,TC/2 if TC even; [TC+1/2],[TC-1/2] if TC odd)
0 1: Square waves of wavelength TC (TC/2,TC/2 if TC even; [TC+1/2],[TC-1/2] if TC odd)
1 0: Single pulse on the TC'th clock pulse
1 1: Single pulse on every TC'th clock pulse.
Asymmetrical Count 5
In case of an odd numbered count, the first half cycle of the square wave output, which
is high, is one count longer than the second (low) half cycle.
Timer Mode Select
Bits 6~7 (TM2 and TM1) of command register contents are
used to start or stop the counter.
TWICE COUNTER
The timer circuit on the 8155 chip is designed to be square wave timer,
not an event counter. To achieve this it counts down by two in
completing one cycle.
Its registers don’t contain the values directly representing the number of
TIMER IN pulses being received,
Counter value ‘1’ can’t be loaded as the initial value in the count register
as the timer operates with the terminal count value of 10.
Twp: 400ns
TIMING DIAGRAMS….
Tpr: 70ns
Trp: 50ns
TIMING DIAGRAMS….
READ CYCLE
T la (min): 80ns (address hold time after latch)
T al (min) : 80ns (address to latch setup time)
Tll (min) : 100ns (latch enable width)
TIMING DIAGRAMS…
WRITE CYCLE
INTERFACING 8085 with 8155
DIMENSIONS (Intel 8155)