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Implementation of NAND NOR AND gates using TTL- Asadullah Hussain & Faizan Khalid

Implementation of NAND NOR AND gates using TTL- Asadullah Hussain & Faizan Khalid

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Published by chachunasayan
Using BJT Transistor Transistor Logic to implement NAND NOR AND gates.
Using BJT Transistor Transistor Logic to implement NAND NOR AND gates.

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Published by: chachunasayan on Jun 30, 2010
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06/12/2013

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Digital Logic Design
Technical Report
1 
IMPLEMENTATION OF LOGIC GATES USING TRANISTOR-TRANSISTOR LOGIC
T
oday the importance of digital circuits cannot be ignored as they make up the basis of moderntechnological living. Digital circuits make use of digital signals that can be stored, duplicated andtransmitted easily.
T
hese digital circuits are composed of units called logic gates which processbinary information. Logic gates are important because practical digital systems involve complexfunctions which can be realized by the use of simple NO
T
, OR & AND functions.
Objective:
Now as these simple functions are fundamental and very important so it is easy to understand thathow the familiarization with these simple logic gates can help us design and make complex digitalpractical circuits.Hence the objective in this project is to familiarize ourselves with the design and construction of these simple logic gates (using
TT
L) and to be able to understand how complex systems can bedesigned by using the technology which is used to construct these simple gates.
IMPORTANT PARAMETERS OF LOGIC GATES:
In designing logic gates there are some terminologies and parameters that an engineer should keepaccount of in order to maximize the performance of digital circuits and optimize the economics of the circuit.
V
oltage transfer characteristic
is an important parameter of logic gates which is the graph of inputvoltage vs output voltage.
T
his graph has four points which are of concern in the design of logicgates.
T
hese are:i.
 
Input low voltage V
IL
(input voltage corresponding to logic 0)ii.
 
Input High voltage V
IH
(input voltage corresponding to logic 1)iii.
 
Output Low voltage V
OL
(input voltage corresponding to logic 0)iv.
 
Output High voltage V
OH
(input voltage corresponding to logic 1)
T
he difference between two output levels is called logic swing:LS=V
OH
-V
OL
Another important parameter is the noise margin which should also be maximized to minimize theerror in processing.
F
an it &
F
an
out refer to the input connections. Fan in is the number of input connections and Fanout is the maximum number of load gates that can be connected to the output.
T
hese numbers are
 
Digital Logic Design
Technical Report
2 constrained by the current loading and switching speed. Apart from these
power dissipation&Transient response
, which when improved can give higher clock frequencies and data rates, areother things that should be kept in mind when designing these circuits.
T
he basis of every digital circuit are transistors which are of different types hence that gives rise tonumerous families of logic gate circuits which can be broadly classified into:i.
 
M
OSii.
 
Saturated Bipolariii.
 
Non-Saturated Bipolariv.
 
Compound semiconductor
Why TTL? 
E
ach of these logic families has unique properties that make it suitable for certain applications.We have chosen
S
aturated Bipolar logic
family in our project.
T
his family includes Resistor-
T
ransistor logic (R
T
L), Diode-
T
ransistor Logic (D
T
L) and
T
ransistor-
T
ransistor Logic (
TT
L).
T
hese usesaturated BJ
T
s as switches.
T
hey have higher transconductance than their
M
OS counterparts, sothey are less vulnerable to capacitive loading.
T
hey outperform
M
OS digital circuits when capacitiveloads are connected such as in case of motherboards.
T
hey also exhibit faster raw speeds than
M
OS.
 
B
 ASIC PHENOMENA:
T
he basic phenomenon used in
TT
L is the use of BJ
T
as a switch and to use BJ
T
as a switch we needto use two modes of operation:i.
 
Cut off mode (In which
E
BJ and CBJ are both reverse biased)ii.
 
Saturation mode (In which both
E
BJ and CBJ are forward biased)
T
o turn the switch ON we use cut off mode.
T
o turn the switch OFF we use saturation mode.In the following section we have implemented AND, NAND and NOR logic gates using
TT
L.
1.
 
NAND
IMPLEME 
 A
TIO
 
 
Digital Logic Design
Technical Report
3 
Image creditswww.elshem.com 
It is the truth table of a typical NAND gate with 3-inputs. We can see that circuit is only LOW when allinputs are HIGH. So to implement this logic function we have following circuit.Z= (A.B.C) `
T
he use of multi-emitter input transistor has solved the problem for multiple inputs and it performsthe ANDing of the input signal. Only in case of all inputs HIGH the transistor becomes reverse active(
E
BJ reverse biased & CBJ forward biased).Hence this input transistor performs the ANDing of thesignal because if only one of the inputs goes LOW then its
E
BJ will become forward biased andtransistor will become OFF as it enters saturation region. So in order for this transistor to be ON allinputs should be HIGH.a.
 
So when
all inputs are HIGH
 
E
BJ of Q1 is reverse biased and CBJ forward biased so it entersreverse active mode.
T
his makes Q 
o
in saturation region, as Q 
o
's base goes HIGH. As weknow that when transistor is in saturation region then it is
O
FF
so V
out
is V
C
E
sat
that is .2 Volts.b.
 
When
any one of the inputs is LOW
then
E
BJ of Q1 is forward biased and it enters saturationregion.
T
his makes Qo in cut off mode. As transistor in cut off mode is
ON
. So output is HIGH.
Improvement:
T
he problem with this circuit is that it requires both Q1 & Qo to discharge once any one of themhas entered saturation region in which minority carriers are injected into base.
T
his dischargingproduced delay in transistor switching. So to remove this problem we use:

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