Extending Logical Networking Concepts in OverlayNetwork-on-Chip Architectures
College of Computer Science and Engineering, Department of Computer Science,Taibah University, Saudi Arabia, P.O. Box 30002Email: email@example.com
—System-on-Chip (SoC) complexity scaling driven bythe effect of Moore’s Law in Integrated Circuits (ICs) arerequired to integrate from dozens of cores today to hundredsof cores within a single chip in the near future. Furthermore,SoC designs shall impose strong requirements on scalability,reusability and performance of the underlying interconnectionsystem in order to satisfy constraints of future technologies.The use of scalable Network-on-Chip (NoC) as the underlyingcommunications infrastructure is critical to meet such stringentfuture demands. This paper focuses on the state-of-the-art in NoCdevelopment trends and seeks to develop increased understandingof how ideal regular NoC topologies such as the hypercube,de-bruijn, and Manhattan Street Network, can scale to meetthe needs of regular and irregular future NoC structures withincreasing numbers of core resources. The contributions of thispaper are three-fold. First, the study introduces a new designframework for overlay architectures based on the success of thehypercube, de-bruijn and Manhattan Street Network in NoCs,providing increased scalability for regular structures, as well assupport for irregular structures. Second, the study proposes howthe regular topologies may be combined to form hybrid overlayarchitectures on NoCs. Third, the study demonstrates how suchoverlay and hybrid overlay architectures can be used to extendbeneﬁts from logical topologies previously considered in opticalnetworks for use with increased ﬂexibility in the NoC domain.
Keywords: Network-on-Chip, logical networks, overlay ar-chitectures, hybrid architectures.I. I
Future performance requirements of networking tech-nologies will be signiﬁcantly different than current demandson performance. Consequently, ultra-fast communication net-work technologies such as optical networks have emergedas a high-bandwidth communication infrastructure for multi-processor interconnection architectures and their presence asan interconnection infrastructure is beginning to emerge inthe NoC literature. Device scaling trends driven by the ef-fect of Moore’s Law suggests that future SoC designs mustintegrate from several dozen cores to hundreds of resourcecores within a single chip, thereby necessitating the needfor increased bandwidth and performance requirements. Theliterature evidences that SoC designs have moved out of bus-based approaches towards the acceptance of a variety of NoCapproaches for interconnecting resource cores.NoC approaches have progressed as the widely adoptedalternative to shared-bus architectures, with the ability tomeet future performance requirements since NoCs supportreusability and network bandwidth scales with system growth[1-7]. This study summarizes the design challenges of futureNoCs and reviews the literature of (some) emerging NoCarchitectures introduced to enhance on-chip communication.An argument is then presented on the scalability and perfor-mance beneﬁts obtained in NoCs by using overlay networks of particular topologies that were previously considered as logicalnetworks for use in optical networks.II. F
The beneﬁts introduced by employing the NoC ap-proach in SoC designs can be classiﬁed as improvements instructure, performance and modularity . The main challengefor NoC designers will be to provide functionally correct,reliable operation of the interacting subsystem components.On-chip interconnection networks aim to minimize currentSoC limitations in performance, energy consumption andsynchronization issues. In [10, 11], the globally asynchronousand locally synchronous (GALS) synchronization paradigmwas identiﬁed as a strong candidate for emerging ICs. GALSeliminates the clock skew in single clock systems by usingmany different clocks in a distributed manner. Thus, thesubsystem components become distributed systems that initiatedata transfers autonomously with little or no global coordina-tion .A key issue in SoC design is the trade-off betweengenerality (i.e. the reusability of hardware, operating systemsand development techniques) and performance (delay, cost andpower consumption in application speciﬁc structures) . Animportant issue is to consider the implications of the NoCdesign approach on the design and implementation costs. Forinstance,  emphasizes that increasing non-recurring costs of NoC-based ICs requires that the design cost of ICs are sharedacross applications, in which case the design methodologywould support product family management.III. R
Various NoC architectures have been proposed to meetfuture performance requirements for intra-chip communica-tion. Essentially, an NoC architecture is the on-chip commu-nication infrastructure consisting of the physical layer, the datalink layer and the network layer. In addition, the NoC architec-ture may be characterized by its switching technique, routing
(IJCSIS) International Journal of Computer Science and Information Security,Vol. 8, No. 1, April 201064http://sites.google.com/site/ijcsis/ISSN 1947-5500