Extending Logical Networking Concepts in OverlayNetwork-on-Chip Architectures
Omar Tayan
College of Computer Science and Engineering, Department of Computer Science,Taibah University, Saudi Arabia, P.O. Box 30002Email: otayan@taibahu.edu.sa
Abstract
—System-on-Chip (SoC) complexity scaling driven bythe effect of Moore’s Law in Integrated Circuits (ICs) arerequired to integrate from dozens of cores today to hundredsof cores within a single chip in the near future. Furthermore,SoC designs shall impose strong requirements on scalability,reusability and performance of the underlying interconnectionsystem in order to satisfy constraints of future technologies.The use of scalable Network-on-Chip (NoC) as the underlyingcommunications infrastructure is critical to meet such stringentfuture demands. This paper focuses on the state-of-the-art in NoCdevelopment trends and seeks to develop increased understandingof how ideal regular NoC topologies such as the hypercube,de-bruijn, and Manhattan Street Network, can scale to meetthe needs of regular and irregular future NoC structures withincreasing numbers of core resources. The contributions of thispaper are three-fold. First, the study introduces a new designframework for overlay architectures based on the success of thehypercube, de-bruijn and Manhattan Street Network in NoCs,providing increased scalability for regular structures, as well assupport for irregular structures. Second, the study proposes howthe regular topologies may be combined to form hybrid overlayarchitectures on NoCs. Third, the study demonstrates how suchoverlay and hybrid overlay architectures can be used to extendbenefits from logical topologies previously considered in opticalnetworks for use with increased flexibility in the NoC domain.
Keywords: Network-on-Chip, logical networks, overlay ar-chitectures, hybrid architectures.I. I
NTRODUCTION
Future performance requirements of networking tech-nologies will be significantly different than current demandson performance. Consequently, ultra-fast communication net-work technologies such as optical networks have emergedas a high-bandwidth communication infrastructure for multi-processor interconnection architectures and their presence asan interconnection infrastructure is beginning to emerge inthe NoC literature. Device scaling trends driven by the ef-fect of Moore’s Law suggests that future SoC designs mustintegrate from several dozen cores to hundreds of resourcecores within a single chip, thereby necessitating the needfor increased bandwidth and performance requirements. Theliterature evidences that SoC designs have moved out of bus-based approaches towards the acceptance of a variety of NoCapproaches for interconnecting resource cores.NoC approaches have progressed as the widely adoptedalternative to shared-bus architectures, with the ability tomeet future performance requirements since NoCs supportreusability and network bandwidth scales with system growth[1-7]. This study summarizes the design challenges of futureNoCs and reviews the literature of (some) emerging NoCarchitectures introduced to enhance on-chip communication.An argument is then presented on the scalability and perfor-mance benefits obtained in NoCs by using overlay networks of particular topologies that were previously considered as logicalnetworks for use in optical networks.II. F
UTURE
N
O
C D
ESIGN
R
EQUIREMENTS
The benefits introduced by employing the NoC ap-proach in SoC designs can be classified as improvements instructure, performance and modularity [4]. The main challengefor NoC designers will be to provide functionally correct,reliable operation of the interacting subsystem components.On-chip interconnection networks aim to minimize currentSoC limitations in performance, energy consumption andsynchronization issues. In [10, 11], the globally asynchronousand locally synchronous (GALS) synchronization paradigmwas identified as a strong candidate for emerging ICs. GALSeliminates the clock skew in single clock systems by usingmany different clocks in a distributed manner. Thus, thesubsystem components become distributed systems that initiatedata transfers autonomously with little or no global coordina-tion [1].A key issue in SoC design is the trade-off betweengenerality (i.e. the reusability of hardware, operating systemsand development techniques) and performance (delay, cost andpower consumption in application specific structures) [5]. Animportant issue is to consider the implications of the NoCdesign approach on the design and implementation costs. Forinstance, [5] emphasizes that increasing non-recurring costs of NoC-based ICs requires that the design cost of ICs are sharedacross applications, in which case the design methodologywould support product family management.III. R
EVIEW OF
O
N
-C
HIP
I
NTERCONNECTION
T
ECHNOLOGIES
Various NoC architectures have been proposed to meetfuture performance requirements for intra-chip communica-tion. Essentially, an NoC architecture is the on-chip commu-nication infrastructure consisting of the physical layer, the datalink layer and the network layer. In addition, the NoC architec-ture may be characterized by its switching technique, routing
(IJCSIS) International Journal of Computer Science and Information Security,Vol. 8, No. 1, April 201064http://sites.google.com/site/ijcsis/ISSN 1947-5500
protocol, topology and node organization. These characteris-tics comprise the design space of future on-chip networks [10].Typically, network functionalities and data transfer propertiesdiffer between on-chip and inter-chip networks, and hence thedesign space for future SoCs must be explored. This sectionreviews the literature of emerging SoC platforms, contrastingdifferences in the design space of each architecture.One particular architecture commonly used as the basisof many NoC design proposals is the 2-dimensional mesh,forming a torus or Manhattan-like topology. In [5], the NoCarchitecture is an m x n mesh of switches and resources. Asimple 2-dimensional topology was selected for its scalabilityand simplistic layout. Consistent with the GALS paradigm,internal communications within each resource is synchronousand resources operate asynchronously with respect to eachother.
Dally et al.
[4] presents a 2-dimensional folded torustopology with the motivation to minimize the total areaoverhead for an on-chip network implementation. The work presented in [10] considers the development of a communica-tions protocol for a 2-dimensional mesh topology using point-to-point crossbar interconnects, with the assumption that thesole user of the network is a programmer. Hence, the network must be able to handle the needs of the programmer and thesurrounding chip environment, therefore requiring support of static and dynamic traffic. In contrast, [2] presents a compar-ison between a bus architecture and a generic NoC model.Principally, the work demonstrates that a NoC-based systemyields significant improvements in performance compared witha bus architecture used in SoC systems.An interesting alternative to the 2-dimensional meshtopology is presented in the literature. For instance, in
Hemaniet al.
[11], the nodes are organized as a honeycomb structure,whereby resources are organized as nodes of the hexagonwith a local switch at the center that interconnects theseresources. The proposed NoC architecture in [11] was generic,it was not tailored to a specific application domain and wasrequired to support re-configurability at the task or processlevel. The work in [11] presents arguments to justify that thearea and performance penalty incurred using the honeycombarchitecture would be minimum.More recently, an interesting area of research hasconsidered the use of multi-processor interconnection archi-tectures that were previously considered for use as logicaltopologies deployed in optical networks for use in NoCs.Figure 1 illustrates a subset of logical topologies consideredhere for use in NoCs. [12] provides an insight as to howany self-routing logical topology may be applied in optical-networks.[7, 12] had considered one particular logical topologyfor use in light-wave physical networks because of its simplerouting and control mechanism. However, a NoC platformwould now imply that the use of logical networks wouldrequire to operate under different constraints and assumptionsfrom those considered earlier in an optical-network environ-ment. The principle of applying a regular logical network, suchas the Manhattan Street Network (MSN), for use as an NoC
,
De BruijnGraphHypercubeManhattan Street Network
,
,
De BruijnGraphHypercubeManhattan Street Network
000001100010011101111110
Fig. 1. A subset of multi-processor interconnection architectures
communications architecture is not new and has been the focusof previous studies [15, 16]. Furthermore, the work presentedin [6, 13] describes the hardware emulation of a regular logicaltopology using Field Programmable Gate Array (FPGA) logicand a hardware emulator. From the study [6, 13], it is notedthat a number of hardware and software design issues mustbe addressed before realizing the hardware implementation of a logical network as an NoC. In the literature, a number of comparisons were drawn with related works which have alsoexplored the NoC implementation of similar torus-like archi-tectures [14] and hierarchical bus-based approaches combinedwith a crossbar NoC architecture [10] implemented on FPGAs.The literature [17-20] presents the hypercube as aregular 3D architecture for SoC interconnection. Whilst severalstudies present arguments of the benefits of such a regularstructure as an NoC, other studies focus on improving ondisadvantages associated with the hypercube [20], yet whilstothers emphasize on the need for irregular NoC structures.The de-bruijn network, on the other hand, presents astronger case for significant performance improvements, scal-ing abilities and support for optimized routing techniques [21-26]. In the literature, several studies had presented variations of the de-bruijn network in order to emphasize its superiority inscaling, reliability, routing, performance, power consumptionand complexity [21 -26], whereas other studies used the de-bruijn network as the benchmark for comparison with otherNoCs, including the butterfly and Benes topology [24] andwith the mesh and torus [23]. All comparative performancemetrics had demonstrated the superiority of the de-bruijn as acommunication architecture for SoCs.This study shall focus on the design and implementationconsiderations of general regular logical networks for use inNoCs in order to extend the topological benefits and findingsfrom mature work on logical topology deployment into theNoC domain. In particular, this study extends the work of logical topology deployment onto general physical networks,and applies an adopted and enhanced concept of overlayinglogical topologies in optical networks for deriving flexibleregular and irregular NoC architectures. Figure 2 illustrates
(IJCSIS) International Journal of Computer Science and Information Security,Vol. 8, No. 1, April 201065http://sites.google.com/site/ijcsis/ISSN 1947-5500
the concept of using logical networks in NoCs.
1 2 345 6 7 89 10 11 1213 14 15 16
1 2 345 6 7 89 10 11 1213 14 15 16
The Regular NoC StructureRemoves the Embedding Problem
cro-eve mpementaton
MSNRegularNetwork
Regular or Hybrid Irregular Networks can bePhysically Implemented or Mapped to the NoC
UnderlyingNoCStructure
,
De BruijnGraphHypercubeManhattan Street Network
,
,
De BruijnGraphHypercubeManhattan Street Network
000001100010011101111110
Fig. 2. Logical Network Implementation on NoCs
IV. M
ETHODOLOGY AND
I
MPLEMENTATION
This paper introduces a new design framework forthe overlay of multi-processor interconnection architecturesthat supports regular and irregular core-numbers on-chip. Arich source of literature exists on the use of multi-processorinterconnection architectures as regular logical networks de-ployed on host optical networks. The motivation here is toapply such logical networking concepts and benefits, throughthe use of the hypercube, de-bruijn and MSN in the SoCdomain, whilst removing the restriction of the highly course-granular regular structure associated with NoC topologies asNoC sizes scale. Therefore, a mechanism for applying overlayarchitectures to support regular and irregular scalable NoCsis introduced as follows. When considering the connectivityand node functionality of each network (see Figure 1), wefind that the in-degree and out-degree for each node is similarthroughout within each network. Hence, from Figure 1, thede-bruijn, hypercube and MSN have a node degree of 2, 3,and 2 respectively (where the in-degree equals the out-degree).Following an overlay of the de-bruijn (as in Figure 3a), forexample, we find two-instances where the functionality of twonodes are ’co-located’ onto a single node (e.g. at the interfacebetween two overlay topologies). The additional functionalityat the co-located nodes may be supported/accommodatedby providing additional buffers that separate network-trafficdestined to graph-1 from traffic destined to graph-2 thenrouting as normal. Different nodes in graph-1 may be co-located to yield various degrees of (comparatively-granular)NoC architectures, therefore providing support for regularand irregular structures (Figure 3b). Figure 4 illustrates thenew NoC architecture after co-location of edge nodes of thede-bruijn network.
1
This paper also extends the conceptof overlay networks to different network-types, producing
1
A similar concept of overlays can also be applied to larger sizes of thede-bruijn, hypercube and MSN. However, this paper has applied the conceptto one-size of each logical topology.
Graph1Graph2
co-locationof edgenodes
(a) (b)Graph1Graph2
co-locationof internalnodes
Fig. 3. Network Overlay concept applied to the De-Bruijn
Graph1Graph2
Fig. 4. The topology produced by overlaying two de-bruijn graphs
a hybrid of overlay architectures. An example in Figure 5demonstrates one hybrid of the MSN and the de-bruijn.The significance of this novel approach to NoC architec-ture design is that it supports performance-intensive tasks to bemapped onto the particularly ideal (high-performance) network segments, such as graph-1 or graph-2, whilst other highly-localized traffic-generating tasks are mapped onto the MSNportion for instance. Hence, this framework also advancesoptimization techniques for application-mapping of tasks ontoNoCs, providing an insight into further opportunities forprogress of key significance in the NoC application-mappingliterature. This section has demonstrated how overlay networksand hybrid overlay networks may be applied to extend thebenefits of logical networks from the optical networks domain(as evident in the mature literature in this topic) to the NoCdomain, while providing support for regular and irregularstructures with comparatively granular flexibility in design.Additionally, the proposed hybrid overlay design enables opti-mization of application-task-mapping onto particular segmentsof the network architecture based on the relative (and signif-icance) of properties for each segment and the correspondingtask-constraints.
(IJCSIS) International Journal of Computer Science and Information Security,Vol. 8, No. 1, April 201066http://sites.google.com/site/ijcsis/ISSN 1947-5500
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Extending Logical Networking Concepts in Overlay Network-on-Chip Architectures
System-on-Chip (SoC) complexity scaling driven by the effect of Moore’s Law in Integrated Circuits (ICs) are required to integrate from dozens of cores today to hundreds of cores within a single chip in the near future.…
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