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Asynchronous Nano-electronics: Preliminary Investigation

Asynchronous Nano-electronics: Preliminary Investigation

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How to make microprocessors using nanowire crossbar arrays.
How to make microprocessors using nanowire crossbar arrays.

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Asynchronous Nano-electronics: Preliminary Investigation
Alain J. Martin & Piyush PrakashDepartment of Computer ScienceCalifornia Institute of TechnologyPasadena, CA 91125, USA
Abstract
This paper is a preliminary investigation in implement-ing asynchronous QDI logic in molecular nano-electronics,taking into account the restricted geometry, the lack of con-trol on transistor strengths, the high timing variations. Weshow that the main building blocks of QDI logic can be suc-cessfully implemented; we illustrate the approach with thelayout of an adder stage. The proposed techniques to im- prove the reliability of QDI apply to nano-CMOS as well.
1. Introduction
Currently, molecular nano-electronics is considered aplausible successor to CMOS. Although immense fabrica-tion difficulties still lie ahead, at least experimental devicesare feasible today. Molecular nano-electronics is a mostlynon-lithographic bottom-up fabrication technology whosemain advantage over CMOS is to break the limit of lithog-raphy in terms of feature size and device density. (Densitiesin the range of 
 ¢¡¤£¦¥
to
 ¢¡¤£¨§
devices per
©§
are mentionedin the literature [2, 3].)All technologies at the nanoscale level, including nano-CMOS,willfacegreatfabricationchallengesthatwilltrans-lateinto important parametervariations anddecreased relia-bility. Timing will be difficult to control and predict. Wireswill be short, by necessity and by choice: the technologydoes not allow to grow long wires reliably and wire delay isquadratic in the length. Consequently, it will be impossibleto build a useful global clocking network with those tech-nologies. For those two main reasons—difficulty in con-trolling and predicting timing and impossibility of buildinga clock network—asynchronous logic seems an ideal andperhaps unavoidable choice for digital circuits in this tech-nology. QDI, which among all types of asynchronous meth-ods, relies on the weakest timing assumption (isochronicfork), seems particularly well suited.This paper is a preliminary investigation in implement-ingasynchronous(QDI)logicinmolecularnanotechnology.It is first and foremost an assessment, and further improve-ment, of QDI’s robustness to extreme parameter variationsand restricted geometry. The paper is organized as fol-lows. First, we brieflydescribethemain featuresof thisnewtechnology. Among several possible alternatives we choosea somewhat idealized one based on complementary FETs.We define its main layout rules. Next, we show how to de-sign basic combinational gates. State-holding elements likeC-elements and precharge function-blocks require some at-tention because the traditional “staticizer” implementationmust be avoided. We give an implementation for thosecells that avoid staticizers. We show how the logic familyof the Caltech Asynchronous Microprocessor(CAM), andthe logic family of the MiniMIPS can be both implementedwithout useof staticizers. We illustrate thedesign style withthe implementation of a ripple-carry adder. Finally, the im-plementation of isochronic forks with its implied timing as-sumption is analyzed.
2. Molecular Nanotechnology
Our targettechnology is asomewhatadvancedversionof thedevicesproduced intheHeathLab atCaltech, theLieberGroup at Harvard and the HP group, [5, 6, 1]. Chemistsare able to grow silicon nanowires (NW) with diametersaround 5nm and up to ten microns in length. These wiresare aligned in one direction, either by a flow process orby nano-imprint. Because of the difficulty in arranging thewires in a regular pattern, the feasible geometry is restrictedto a crossbar: a collection of parallel wires in one directionsuperimposed with a collection of parallel wires in the or-thogonal direction. However, the grid is not perfectly regu-lar and several wires may be broken.Interesting things may be made to happen at the intersec-tion of two orthogonal wires. Special molecules (e.g. ro-taxane) can be placed at the crosspoint between two wiresto connect the two wires. Such a junction is originally of high enough resistance that the two wires are not electri-cally connected. But, if a high voltage is applied between
 
the two wires, the molecule will begin conducting and con-tinue to do so when the voltage is lowered. In other words,by applying voltage at selected junctions, the junctions canbe programmed to conduct. The junctions can also be madeto rectify, i.e., we can program both resistors and diodes.Resistors and diodes are sufficient to build a completelogic family and have been used to build PLAs and mem-ories, but they have no gain (amplification) and thereforesignal degradation is unavoidable, leading to failure in anycomputation containing a significant number of transitionsin series. In order to implement general computations, tran-sistors are needed to provide amplification, which in turnrequires to be able to make semi-conductors out of siliconNWs. NWs can be doped during the growth in order to con-trol their conductivity. Heavily doped regions of a wire areconducting; some regions can be kept lightly doped so as tocontrol their conductivity via an electrical field created byapplying a voltage on the crossing metal wire. If a dielectriccan be placed at the intersection of (and between) the twowires, one has effectively created a FET at the junction. (Sofar no technology offers programmable FETs, unlike resis-tive junctions and diode junctions.)Technologies with one type of transistors (usuallypFET),diodes,and resistivepullupsor pulldownshavebeenannounced and demonstrated. The transistors have enoughgain to build restoring logic. Recently, all three groupsmentioned have announced that they will soon (or alreadydo) fabricate FETs of both n- and p-types, with appropriatethreshold voltages and acceptable gain, making it possibleto design complementary logic circuits.Although the characteristics of the transistors are stillshrouded in mystery, we take as working hypothesis thatsuch devices will be built. We also assume the availabil-ity of low-resistance metal wires for the grid direction thatprovides the gates of transistors. (Such metal wires areobtained either by coating silicon wires with metal duringcrystal growth, or by imprinting pure metal wires using thenano-imprint technique.)Let us summarize the components of our (slightly pre-cursory) target technology. As already mentioned, we be-lieve that most properties of this technology will apply tonano-CMOS. The basic building block is the tile. A tileis a crossbar array of nanowires: the (top) horizontal wiresare metal conducting wires that are used as gates of tran-sistors; the (bottom) vertical wires are semiconducting sili-con nanowires (NW) used as channels of transistors. Wirelength is strictly limited, say around
 ¡
m, with a wire-to-wire pitch of approximately
 ¡
nm. (Metal wires can bepacked more densely and can be longer as they are less re-sistant. But we will ignore those differences.) We assumethat we can implement tiles of 
 ¡¡¡¡
wires.A tile may be a routing tile or a compute tile. A routingtile contains only programmable junctions and is used toconnect two compute tiles. A compute tile consists of an
n- plane
, a
p-plane
, and a
routing plane
. An n-plane containsn-transistors only; a p-plane contains p-transistors only; arouting plane contains programmable connections only.An importantadvantageof thistechnology is thatthe dif-ferent active crosspoints (transistors, resistors, diodes) fitexactly under the area of the crosspoint and therefore donot increase the area of the array, hence contributing to thedensity advantage of the technology.A fewimportantrestrictions andproperties mustbemen-tioned. (1) It is not possible tomix thedifferentcomponents(n-transistor, p-transistor, resistor) inside the same plane.Each plane is homogeneous. (2) It is not possible to con-nect wires end-to-end in one direction. Connections aremade through orthogonal wires. (3) Connection resistanceis high (100K
) and highly variable. (4) The drive of tran-sistors is not well characterized. We assume that the limitto the number of transistors in series is similar to CMOS.We have chosen 3 as a hard limit. (5) Up to 10% of thewires and connections may be broken or stuck open. (6)Finally, the collection of nano-tiles is placed on top of astandard silicon layer. Power distribution and input/outputare implemented in the silicon layer. All vertical nanowiresin a p-plane are connected to a micro-wire distributing Vdd,and all vertical nanowires in an n-plane are connected to amicro-wire distributing GND.
3. Implementing QDI Logic
Among all asynchronous logic families, QDI is the mostrobust to parameter variations because it relies on the weak-est timing assumption: the
isochronic fork 
. The main ques-tion addressed in this paper is the following. In the presenceof extreme PVT (process, voltage, temperature) parametervariations, how will a QDI circuit (implemented in molecu-lar nano) fail, and what can be done to avoid the failure orat least significantly improve the circuit’s robustness?
"!$#%!'&)(1032  54$687@9A4B(C6D7FEG&IHPE$ERQ
The implementation of combinational cells does notpresent any particular problem beside the usual restrictionon the length of transistor chains, but it gives us the oppor-tunity to fix a general layout scheme. Figure 1 shows twoalternative implementations for the inverter and the nand2.(The nor2 gate is derived form the nand2 by exchangingVdd and GND, and p- and n-transistors.) A dot at the inter-section of two wires indicates a connection, a diagonal bar(/) indicates an n-transistor. A diagonal bar (
S
) indicates ap-transistor. In the first type of layout, the n- and p-planesare vertically aligned w.r.t. the metal wires; in the secondtype, they are horizontally aligned w.r.t. the metal wires. It
 
b
0
~A~AA+ 0+ApFETnFETConnectionKey:Metal wireSiliconChannel0
c
+ +c0aab
Figure1. Twopossible layouts forthe inverterand nand2
is clear that the second choice of layout presents an impor-tant area advantage: the area of the nand-gate is 6x3 in thefirst case and 2x3 in the second case. As shown in Figure 2,the area penalty of the first layout for an n-input combina-tional gate is
TU§
. But there is another, more important, ad-vantage to the second layout choice. If an input is shared byseveraltransistor gates, then inthesecondlayoutchoice, theinput signals to the different gates are carried by the samemetal wire, resulting in very similar
VXW
characteristics forthe different paths. In the first layout choice, the paths fromone input to severaltransistor gates are very dissimilar, withthe paths to one type of transistors going through two resis-tive contacts and the paths to the other type of transistorsbeing a single metal wire. As we shall see, this differenceis important for the implementation of isochronic forks.
"!`YC!bacHP6DHPde7FEgfb7ih%(Cp"9cqsrut8Hv0wH
The general scheme for a compute tile is shown in Fig-ure 3. The two transistor planes are side by side with theinputsignals running horizontally on metal wires. Each ver-ticalsemiconductor wire of thetransistor planes can beused(inside a transistor plane) as a pullup or pulldown transistorchain if transistors are placed at some of the cross-points.Because of the restricted geometry, parallel chains cannotshare transistors, and therefore all boolean expressions areimplemented in the disjunctive normal form: The expres-sion
xbyR")©
can only be implemented as
xgys)xXy©
.The general shape of the routing plane is that of an invertedT as shown on the figure. The part of the routing plane be-tween the twotransistor planes is used onlyfor the feedback connections needed in the implementation of state-holdinggates. (We will give examples shortly.) The bottom part of the routing plane connects the pullup and pulldown chainsto the output(s) of the logic gate. (A similar scheme hasbeen proposed in [1].) A single compute tile contains sev-eral cells.
inputs
pn
n2n overhead
2
no overhead
pn
Figure 2. Two possible layouts for an n-inputcell
+nplane pplanerouting plane0
Figure 3. General layout scheme for a com-pute tile

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